Dipartimento di Elettronica Informatica e Sistemistica
Research topics


C. Metra
Collaborations: Intel Corporation, Santa Clara



C. Metra

Collaborations: Università di Padova


C. Metra

Collaborations: Simon Frasier University (Vancouver, Canada)



C. Metra

Collaborations: Government College of Technology (Coimbatore, India)



C. Metra



E. Gnani

Collaborations: Texas Instruments, Dallas, TX, Semiconductor Research Corporation (SRC)


E. Gnani

Collaborations: UCL (Louvain La Neuve); University of Glasgow; Synopsys Switzerland (Zurich); Micron Technology (Agrate), IUNET (UniPI, UniUD, UniBO).


E. Gnani

Collaborations: University of Pisa, University of Udine, AMO (Germany), CEA-LETI (France), TNI-UCC (Ireland), University of Cambridge (UK).


E. Gnani

Collaborations: University of Pisa, University of Udine, IBM (Switzerland), CEA-LETI (France), EPFL (Switzerland), University of Juelich (Germany), TU Aachen (Germany), Globalfoundries (Germany), Intel (Germany).



E. Gnani

Collaborations: Institute of Microelectronics IME (Singapore).



M. Tartagni


M. Tartagni

Collaborations: University of Southampton (UK), KTH (S)


F. Filicori, A. Santarelli, R. Cignani, D. Niessen

Collaborations: Selex Sistemi Integrati, Thales Alenia Space, Università di Ferrara, IEMN, Lille (France), Università di Roma Tor Vergata, Università di Firenze, Università di Torino, ESA.


F. Filicori, A. Santarelli, C. Florian, R. Cignani, D. Niessen

Collaborations: IEIIT-CNR, Bologna, Università di Ferrara, Università dell’Aquila, Thales Alenia Space, ASI, ESA.


F. Filicori, A. Santarelli, C. Florian, R. Cignani

Collaborations: SIAE Microelettronica, Milano. UMS, Orsay, France. ASI, WIN Semiconductors, Triquint Semiconductors



F. Filicori, C. Florian

Collaborations: Università di Modena. MEC s.r.l., Bologna.



F. Filicori

Collaborations: Dipartimento di Ingegneria Elettrica, Università di Bologna. Dipartimento di Elettronica, Università di Firenze. Thales Alenia Space Italy. MIUR.



C. Metra

In any synchronous system, clock is one of the most critical signal, since it has to be distributed throughout the chip by means of a complex clock distribution network. With the continuous increase of clock frequency allowed by the advances in microelectronic technology, it is becoming increasingly more difficult to guarantee the availability of correct clock signals throughout the chip.

By means of inductive fault analysis performed starting from defect statistics, it has been shown that faults affecting the clock distribution network are likely, and that their effects (mainly skew and duty-cycle variations) can be catastrophic for the microprocessor operation in the field. Unfortunately such effects can be neither detected through conventional structural testing, nor compensated by current calibration and correction schemes.

These problems can only worsen with the scaling of technology, because of the increasing likelihood of manufacturing defects and process variations, as well as the larger manufacturing die size and higher clock frequency.

To deal with these problems, self-checking detectors for clock faults and self-correcting clock buffers have been proposed. Although they are intended to detect/correct clock faults affecting the microprocessor operation in the field, they can be employed also for clock faults' manufacturing test. However, especially if employed at the local level of the clock distribution, they may imply a non-negligible cost in terms of design, routing and power consumption. While these costs may be acceptable to high reliability applications, microprocessors for general purpose applications would prefer lower cost approaches, at least during manufacturing test.

In collaboration with Intel Corporation, Santa Clara, we analyzed the problem of on-chip clock jitter measurement with minimal impact on area and performance.

We developed an on-chip clock jitter digital measurement scheme for high performance microprocessors. The scheme enables in-situ jitter measurement of the clock distribution network during the test or the debug phase. It provides very high measurement resolution, despite the possible presence of power supply noise (constituting a major cause of clock jitter) affecting itself. The resolution is higher than a min sized inverter input-output delay, obtained at a very low area and power cost.



C. Metra 

Traditionally, fault tolerant techniques have been used to combat the uncertainty in the signals on and from the ICs of systems for high reliability applications, (e.g., space, transport, automotive, etc.).

In fact, signal integrity problems are becoming increasingly critical, due to the power supply reduction, the shrinking of devices physical dimensions, and the increasing of the operating frequencies (up to several GHz), requiring the implementation of fault tolerant techniques. The disadvantage of applying traditional fault tolerant approaches is that they generally imply a non-negligible impact on performance and an increase of area overhead, thus causing also a severe decrease in yield, hence rise in cost, and a three-fold increase in power consumption. Consumer electronics, of course, cannot afford the high cost of traditional fault-tolerant techniques. To enable the trend towards further miniaturization, while maintaining the reliability of the electronic system, a new way has to be found to deal with possible errors. In particular, hard errors, mainly due to the fabrication process, and soft errors are among the major problems forecasted by the Silicon Roadmap for next generation electronics components. A promising approach to cope with the mentioned issues is to move towards innovative fault tolerant approaches which, relaxing the requirements for 100% correctness in both transient and permanent failures of signals, logic values, device, or interconnects, may reduce the cost of manufacturing, verification and test.

More recently, due to the aggressive scaling of oxide thickness and the consequent large vertical electric fields in MOSFET devices, devices characteristics are considerably degrading. One of the main concerns is the significant threshold voltage shift over time, particularly due to Negative-Bias Temperature-Instability (NBTI), thus creating additional uncertainty in the device behavior. NBTI is recognized as the primary parametric failure mechanism in modern ICs. It is characterized by a positive shift in the absolute value of the pMOS threshold voltage, mainly due to the creation of positively charged interface traps, when the transistor is biased in strong inversion. Due to this phenomenon, the absolute threshold voltage can increase by more than 50mV over ten years, resulting in more than 20% circuit performance degradation. This detrimental effect of NBTI mandates an accurate modeling of this phenomenon, as well as the development of ad hoc technique to detect it before it leads to an erroneous behavior of the system.

Within the above-mentioned research collaboration projects, we addressed the issue of developing new fault tolerant approaches to protect electronics components and systems against hard and soft errors, with minimal impact on performance, power consumption and area overhead. Moreover, we focused on developing novel monitoring techniques for aging effects, as  well as new approaches to tolerate/mask their detrimental effects.


C. Metra

Although batteries are still the most widespread powering system for today’s portable and wearable electronics, they are not suitable to power the biomedical applications considered here. In fact, they are still too much cumbersome and heavy to be possibly integrated into wearable medical devices,  which should remain 24 hours a day perfectly adherent to the body of a person.

Additionally, although battery life time significantly improved in the last years, they still need to be replaced or properly recharged, with consequent interruption of service of the powered device, which is not acceptable for the biomedical applications considered in this project. Consequently, alternative powering systems should be conceived. As for battery alternative powering systems, in recent years we have witnessed an increasing interest on energy harvesting approaches. Although they are still under study and experimentation, they might fit well the size and weight needs of our applications.

Particularly, those exploiting the human body as an energy source (through the heat and the movement) seem a natural solution for the applications considered here.

Like any other electronic system, energy harvesting systems are prone to get affected by faults, which might make them fail in providing, with no interruption, their intended service, thus making them unreliable. Therefore, proper design approaches need to be devised, in order to guarantee the reliable operation of the energy harvesting system, which is in turn mandatory for the reliable operation of the to-be-powered system, despite the possible (and unavoidable) occurrence of faults affecting the energy harvesting system itself.

Such faults may occur because of material aging during usage, as well as be induced by the everyday life environment, for instance due to electromagnetic interference with mobile phones, notebooks, etc., not to mention all particle- induced faults that electronic devices experience when on-board of aircrafts.

Such faults might make them (and the to-be-powered systems as well) completely unable to operate. In case of systems for biomedical applications of the kind considered in our project, this would obviously have catastrophic consequences.

In collaboration with Simon Frasier University (Vancouver, Canada), as a case study, we considered a wireless biomedical sensor node designed to monitor human vital signs. The sensor is self-powered by an energy harvesting circuit from human breathing, which uses a piezoelectric generator to convert the energy of mechanical vibrations into electricity.

We analysed the effects of faults possibly affecting the considered energy harvesting system, showing that they make the energy harvesting circuit fail in producing the correct power supply voltage level. An additional circuit has been proposed, to monitor the provided power supply voltage, concurrently with the sensor normal operation. This additional circuit implies very low increase in power consumption and negligible area overhead compared to the original energy harvesting system. It generates an error indication if the provided power supply voltage falls below the minimum voltage value that is required by the sensor to work properly. Upon the error message generation, a long-term recovery procedure can be activated, for instance implemented by the automatic power switch to a small integrated rechargeable battery, till system repair.


C. Metra

Modern microprocessors ability to process large amounts of data and implement advanced digital signal processing is increasingly enabling the successful deployment of advanced control systems based on remote sensing and measuring.  This is opening a widespread range of new opportunities to control the environment, wildlife habitats, complex industrial plants, aerospace vehicle platforms, etc.

Wireless personal area networks (WPANs), defined by the IEEE 802.15.4 standard, are widely adopted within the abovementioned applications, because of their low complexity and cost. One important issue for WPANs is their security, in terms of confidentiality, integrity, authenticity, availability.

An effective key management system is important in the WSN environment as it reduces the communication overheads of sensor nodes. This in turn reduces the battery consumption and increases the life span of such devices. There are lots of key distribution scheme, Public key cryptography mechanism is one among them and well suited for key distribution. But this public key cryptography involves in large number of mathematical computation. As already said, the nodes have limited amount of energy since it is battery operated, using public key cryptography mechanism the nodes consumes energy in order to perform mathematical computations, and are not suitable for WPAN. Private-key cryptography is suited for WPAN due to its low energy requirements. Key distribution is usually done off-line before deployment of nodes. Once the nodes are placed, they can communicate each other and compute a common key for highly secured data exchange among the nodes.

We have developed a polynomial based key distribution scheme for secure communication protocol that, using a simple hardware and minimum number of polynomials, allows the generation of a large number of keys. A set of polynomials is stored in all the nodes, and the initial seed is to be generated in each node. The key is generated using 128bit LFSR (Galois Type) that uses the primitive polynomial and initial seed to generate the 128 bit sequence. For each and every communication the seed and primitive polynomial is varied, hence a variety of key can be generated using simple hardware. Using 128 bit LFSR, 2128-1 sequences can be generated. For a 100GHz system, it requires 1012 years to circulate all possible sequences. Since different keys were used for each transmission, the number of encrypted data available in free space (channel) for an attacker (for cryptanalysis) is smaller than the other schemes with shared keys for all nodes.



C. Metra

In the recent years, photovoltaic (PV) systems have been increasingly adopted as a promising source of green energy. In fact, according to the European Photovoltaic Industry Association, notwithstanding the global financial crisis, the PV market has grown significantly. Currently, after hydro and wind power, PV power  is the third most important renewable energy source, showing an energy volume sufficient to cover the annual power needs of over 20 million houses in the world. Under this scenario, the demand for reliability of PV systems is continuously increasing. In fact, considering that PV systems are becoming to be perceived as a form of economical investment, the longer is their reliability, the smaller are the maintenance costs, with consequent higher economic benefits to the investors.

When employed in an urban environment, shading of the PV array from nearby obstructions, such as trees, telephone poles, antennas, bird droppings, neighboring buildings etc., or even self-shading of adjacent arrays, can lead to energy output losses. More dangerously, as specified later in the paper, shading of a PV cell, or group of cells, can also lead to a phenomenon denoted as hot-spot, which can produce a permanent damage of the shaded area, with a consequent reduction of the provided power.

Hot-spot is produced when one (or more) PV cells within a PV array is partially shaded, with a consequent mismatch in the radiation of the PV cells of the array. Under this condition, the non-shaded part of the array operates at current levels higher than those of the shaded PV cell or group of cells. As a consequence, the affected cell, or group of cells, is forced into reverse bias, thus starting to dissipate power, with a consequent temperature increase. This phenomenon can cause overheating (hot-spot) and possible permanent PV cell damages, if the shading condition is not removed before the cell temperature reaches a critical value.

Based on these considerations, we have developed a model to estimate the temperature of a PV cell as a function of the time interval in which such a PV cell is under a hot-spot condition. Our proposed model is validated against experimental results. We have verified that the time interval required to reach a critical temperature, making the hot-spot produce permanent damage in the affected PV cell, is strongly influenced by the shadowing grade, irradiation intensity and ambient temperature, as well as by the concentration of impurities in the materials. Our model can be successfully used to evaluate the maximum time interval in which a PV cell can remain under a hot-spot condition, without suffering from permanent damages. The evaluation of such a time is a preliminary step towards the development of shading tolerant techniques which, if activated in the field, could avoid PV cell damage in case of shading, thus avoiding consequent efficiency loss of the whole PV array.


Pubblications 2011

1)         C. Metra, M. Omaña, TM Mak, S. Tam, “Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors”, IEEE Transactions on VLSI Systems, Vol. 19, No. 12, pp.  2322 – 2325, December 2011.

2)         D. Rossi, N. Timoncini, M. Spica, C. Metra, “Error Correcting Code Analysis for Memory High Reliability and Performance”, IEEE Proc. of the Design, Automation and Test in Europe (DATE), 2011.

3)         D. Rossi, M. Omaña, C. Metra, A. Paccagnella, “Impact of Aging Phenomena on Soft Error Susceptibility”, IEEE Proceedings of the IEEE Int. Symp. on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’11), 2011.

4)         D. Giaffreda, M. Omaña, D. Rossi, C. Metra, “Model for Thermal Behavior of Shaded Photovoltaic Cells Under Hot-Spot Condition”, IEEE Proc. of the IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'11), 2011.



E. Gnani

Linear BICMOS and Smart-Power Technologies typically allow for the integration of medium-to high-power devices on chip, which are meant to fabricate output drivers operating at relatively high voltages (typically 20-100 V). These devices are either Lateral or Vertical Diffused MOS transistors (LDMOS, VDMOS). LDMOS are often preferred since their breakdown voltage can be adjusted to the circuit requirements by layout and/or minor implant changes, as opposed to VDMOS whose breakdown voltage is strictly related with the epi-layer thickness. The area consumption of such devices is often exceedingly large, and represents a fair fraction of the overall chip area for analog/mixed-signal applications. Therefore, their optimization is highly relevant from the standpoint of the product cost effectiveness. The fundamental device constraints are the on-resistance and the breakdown voltage, which clearly represent conflicting goals. Increasing the breakdown voltage implies extending the lateral drift region and/or reducing the doping density in that region, at the expense of the on-resistance. In view of the above considerations, it turns out that a careful device optimization based on an extended use of calibrated simulation tools is an important aspect of the high-performance, low-cost solutions requested by RF and analog/mixed-signal applications.

This project aims to optimize the on-resistance versus breakdown voltage trade-off in the 20-100 V range, albeit keeping manufacturability and reliability in foreground.

The proposed methodology is based on the use of extensive TCAD simulations of the following three main device concepts: i) planar lateral MOSFET;s ii) trench lateral MOSFETs and, iii) trench up-drain vertical MOSFETs, which have been identified as the most promising candidates for linear BICMOS and Smart-Power technology applications. Modeling chal-lenges have been identified in relation with the 3D nature of some of the concepts and in the TCAD analysis of hot-carrier-stress (HCS) degradation.

This work has been carried out in strict cooperation with TI, which provided experimental data on existing technologies and the relevant information on device geometry and morphology.

Selected concepts have been implemented by TI on test chips to assess feasibility and performance and to refine TCAD modeling.

The reference LDMOS device, based on shal-low-trench isolation (STI), has been widely investigated through both experimental and numerical studies in the first phase of the project. A first interesting and cost-effective way to improve the RSP vs. VBD trade-off is represented by the multi-STI-finger LDMOS (MF-LDMOS) structure, based on a layout variation with interleaved silicon/STI fingers along the drift region. A proper design led to a beneficial improvement of the breakdown voltage (+16%) for a fixed on resistance. The analysis of the HCS reliability has been focused on the degradation of the main electrical parameters, i.e., the linear and saturation current, the maximum transconductance, and threshold-voltage shift for both the reference and MF-LDMOS. The simulation of the time-dependent trap formation at the interface has been carried out on a reference device first, and experiments have been nicely reproduced by the numerical results. The spatial distribution of the simulated interface trap density shows that most of the degradation occurs at the source-side corner of the STI. When moving to devices with larger VDD, an additional contribution of degradation close to the drain side of the STI is observed, fully explaining the experimental trends. The same TCAD approach has been successfully applied to the study of the degradation curves of the multi-STI-finger LDMOS (see figure below). The simulated interface-trap distribution clearly revealed the detrimental impact of the interface degradation along the silicon fingers.

Pubblications 2011

1)         S. Reggiani, S. Poli, M. Denison, E. Gnani, A. Gnudi, G. Baccarani, S. Pendharkar, R. Wise, “Physics-based analytical model for HCS degradation in STI-LDMOS transistors", IEEE Transactions on Electron Devices, Vol. 58, no. 9, pp. 3072-3080, 2011.

2)         S. Poli, S. Reggiani, M. Denison, E. Gnani, A. Gnudi, G. Baccarani, S. Pendharkar, R. Wise, “Temperature dependence of the threshold voltage shift induced by carrier injection in integrated STI-Based LDMOS transistors", IEEE Electron Device Letters, Vol. 32, no. 6, pp. 791-793, 2011.

3)         S. Poli, S. Reggiani, R.K. Sharma, M. Denison, E. Gnani, A. Gnudi, G. Baccarani, “Optimization and Analysis of the Dual N/P-LDMOS Device", IEEE Transactions on Electron Devices, 2011.

4)         S. Poli, S. Reggiani, M. Denison, G. Baccarani, E. Gnani, A. Gnudi, S. Pendharkar, R. Wise, “Full Understanding of Hot-Carrier-Induced Degradation in STI-based LDMOS transistors in the Impact-Ionization Operating Regime", ISPSD 2011, San Diego, California, pp. 152-155.

5)         S. Poli, S. Reggiani, R. K. Sharma, G. Baccarani, E. Gnani, A. Gnudi, M. Denison,”TCAD optimization of a dual N/P-LDMOS transistor", ESSDERC 2011, Helsinki, Finland, 2011, pp. 247-250.

6)         S. Poli, S. Reggiani, G. Baccarani, E. Gnani, A. Gnudi, M. Denison, S. Pendharkar, R. Wise, “Hot-carrier stress induced degradation in Multi-STI-Finger LDMOS: An experimental and numerical insight", Solid State Electronics, Voll. 65-66, no. 1, pp. 57-63, 2011.



E. Gnani

The microelectronic industry has relied on shrinking transistor geometries for improvements in circuit performance and cost per function over three decades. Continued transistor scaling will not be as straightforward in the future as it has been in the past, because fundamental materials and process limits are rapidly being approached in the bulk Si-CMOS tech-nology.

Innovative device structures and new materials are needed to continue improving the device performance. Non-classical silicon MOS structures, such as ultra-thin-body SOI or multi-gate transistors like, e.g., FinFETs can be scaled more aggressively than the bulk-Si structures, and may thus be considered in future technology nodes.

Despite the importance of the above aspects, a com-prehensive simulation tool including all the relevant is-sues on the transport models has been lacking so far. Carefully calibrated quantum drift-diffusion simulations can still be used to study not only the performance of the new devices but also the role played by individual and combined variability sources on transport, in particular those related to the random body thickness variations in ultra-thin body SOI and FinFETs, those induced by the random oxide thickness variations and, finally, those induced by local variations of stress.

This project aims to develop a carrier mobility model, suitable for device simulation tools, which includes the effects of different crystallographic orientations, different gate stacks, thin oxides, and complex strain con-figurations. The new model will be also adopted to accu-rately describe the impact of variability and reliability on the device performance.

In order to define an analytical mobility mo-del suitable for device-simulation tools based on the drift-diffusion equations, a two-step procedure has been fol-lowed. In the first step, an analytical model for the effective mobility as a function of the effective electric field and inversion-charge concentration per unit area has been developed. The effective mobility has been calibra-ted over a wide set of experiments carried out on long-channel devices. In the second step, a local mobility model, which depends on the local normal electric field and on the local electron concentration, is provided.

An easy-to-implement electron and hole mobi-lity model that accurately predicts low-field mobility in the channel of ultra-thin-body FETs fabricated on different crystal orientations has been developed by this unit. The investigation has been extended to FinFETs. At a first step, the effective mobility can be written as the average of the effective mobilities in the top and sidewall channels. For widths below 75 nm, the rounding of the fin corners is taken into account by assuming a (111) orientation.

Finally, an extensive simulation analysis of silicon nanoribbon field-effect transistors for the detection of chemical warfare agents has been performed through investigation of the physical behavior of the device. An accurate modeling of the nanoribbon interfaces has been carried out before and after gas exposure by combining simulation, characterization techniques and validation against experiments. A quantitative description of the physical mechanisms involved in the gas detection has been obtained.



E. Gnani

The exfoliation of graphene in 2004 has opened up an exciting research field, attracting many scientists both on the physics and the engineering side. This is due to the graphene unique properties, some of them very promising for nanoelectronic applications, such as its huge room-temperature carrier mobility (exceeding 105 cm2/Vs in suspended graphene) and its monoatomic thinness. These properties are the key for manufacturing FETs which are fast and robust against short-channel effects. On the other hand, graphene is a zero-bandgap semiconductor, and this poses severe limit-ations to the final transistor performance. One way to circumvent this problem is the use of nanometer-wide graphene nanoribbons (GNR), in order to exploit the lateral quantum confinement to open an energy bandgap.

So far, most of the research efforts on GNR-FETs have been directed towards digital applications. However, it has been found that poor on/off current ratios are obtained unless extremely narrow (< 3 nm) GNRs are used as the channel material. In such narrow GNRs, besides the obvious fabrication challenge in an industrial process, increased phonon scattering and, most import-ant, edge defects greatly reduce the carrier mobility ultimately spoiling the speed advantage. On the other hand, in analog applications, where the FET is used as a transconductor, the on/off problem is much more relaxed and the potential of graphene can be much better exploited. For this reason, several research groups worldwide are working towards the optimization of graphene devices for analog applications, such as high-frequency amplifiers (low-noise and power amplifiers), or even other devices directly exploiting the ambipolar behavior of graphene (e.g. frequency doublers).

The activity reported here aims at the development of a suitable simulation tool for graphene FETs (from narrow GNRs to extended graphene devices) and its use for the optimization primarily of analog device performance.

The modeling approach is based on an in-house developed code which self-consistently solves the quantum transport problem and Poisson’s equation. The Non-Equilibrium Green’s Function (NEGF) formalism is used for quantum transport. The Hamiltonian can be either based on the atomistic tight-binding (TB) approximation, with one pz orbital and nearest neighbor interactions, or on the effective mass approximation with non-parabolic corrections. Recently, a thorough investigation has been carried out with the aim of identifying proper ways to include phonon scattering (both elastic, i.e. acoustic, and inelastic, i.e. optical) in a way fully consistent with the TB approach. The effect of such scattering terms in complete devices has also been investigated. Edge defects can be simulated by randomly adding or removing atoms pairs along the edges.

The above code has been applied to the  simulation of GNR-FETs intended for high-frequency analog applications. In order to avoid the already mentioned problems related with very narrow ribbons, the width of the simulated GNRs has been chosen in the 10-15-nm range, corresponding to 80-140-meV energy-gap. Such a band-gap is still too small even for analog applications, in that it is responsible for the absence of a well-defined saturation region in the output characteristics and, hence, for a large output conductance. The latter, in turn, limits the maximum obtainable small-signal voltage-gain. The origin of such effect can be traced back to the onset at high VDS of band-to-band-tunnelling between channel and drain. Through the use of simulations, some design criteria have been identified which help reduce the problem and increase the maximum voltage-gain: i) asymmetric doping between source and drain (ND < NS), ii) very small EOT (through the use of high-k dielectrics), iii) proper doping profiles in the underlap drain region, iv) electrostatic doping of the underlap drain region through the use of multiple gates with different work-functions. Following these criteria, GNR-FETs with AVmax> 30 and fT > 1 THz can be achieved.

Recently, simulations of FETs based on an extended graphene layer have been performed, aimed at understanding the origin of the experimentally observed negative differential resistance and at the optimization of the device characteristics for analog applications. The effect can be traced back to the contact junctions


Pubblications 2011

1)         I. Imperiale, A. Gnudi, E. Gnani, S. Reggiani, G. Baccarani, “High-frequency analog GNR-FET design criteria”, Proc. ESSDERC 2011, 12-16 Sept. 2011.



E. Gnani

Power consumption has long been, and still is, the most important limitation for high performance logic. For this reason, the clock frequency of advanced processors has not improved over 4 GHz, and further progress is being sought at the architectural level by exploiting parallelism. The growth of power consumption over the years is due to several reasons: i) the supply voltage has not been scaled in direct proportion with the feature size; ii) the static power dissipation due to channel leakage grows exponentially with the reduction of the threshold voltage and, iii) the gate oxide has become leaky due to electron tunneling. While the latter problem has been addressed by working out high-κ dielectrics, the two former issues are related with the non-scalability of the subthreshold slope which has not found any viable solution yet. The objective of a current turn-on rate much steeper than 60 mV/dec has been pursued by several approaches, which can be classified in two main categories. The first class of devices is based on the introduction of a positive feedback in the turn-on mechanism. The next device class is based instead on a filtering of the high-energy electrons injected into the channel, where the filtering function is demanded to the band-to-band tunneling.

In this research line we propose an approach for steep subthreshold-slope FETs which is based on a filtering of the high-energy electrons entering the device channel. The filtering function is pursued by shaping the density of states within the source extension by engineering the semiconductor band structure, so as to generate a first subband with a small energy extension, and a second subband widely displaced in energy, so that its contribution to the drain current is nearly negligible.

The exponential increase of the FET subthreshold current with an inverse slope of at most 60 mV/dec is rooted in very basic thermodynamic principles, namely Fermi statistics. As Fermi statistics cannot be changed, we intend to shape the density of states within the conduction band, so that current injection into the device channel is prevented in subthreshold. This goal can be achieved by a special injector in the source extension of a nanowire FET with the ability to filter out high-energy electrons, and we propose to implement this filtering function by a superlattice. As for the Krönig-Penney potential, the conduction band of a superlattice is split off in a number of minibands whose parameters (lower energy of the first miniband, energy extension of the first miniband, and energy gap between the lowest and the second-lowest miniband) can be optimized for optimal performance by selecting a suitable material pair and by adjusting the superlattice geometrical parameters, i.e. the barrier and the well widths.

The investigation has been carried out by developing a simulation code with the ability to solve the coupled Schrödinger-Poisson equations within a composite NW-FET structure incorporating a superlattice. Such an investigation has proved that the superlattice minibands are nearly coincident with the subbands predicted by the Krönig-Penney model, so that the band structure optimization can be carried out using such a model. The device turn-on characteristics exhibit inverse subthreshold slopes well below the limit of 60 mV/dec and the output characteristics show a large drain conductance at low drain voltage, as required by logic circuits.

The choice of the material pair defines the band offset and the electron effective masses within the two semiconductors of the superlattice. Preliminary simulations have been carried out with no optimization for several material pairs, including GaN-AlGaN, InGaAs-InAlAs and InGaAs-InP.


Pubblications 2011

1)         E. Gnani, P.Maiorano, S. Reggiani, A. Gnudi, G. Baccarani, “Performance limits of superlattice-based steep-slope nanowire FETs”, Proc. IEDM 2011.

2)         E. Gnani, P.Maiorano, S. Reggiani, A. Gnudi, G. Baccarani, “An investigation on steep-slope and low-power nanowire FETs”, Proc. ESSDERC 2011, 12-16 Sept. 2011.

3)         E. Gnani, P.Maiorano, S. Reggiani, A. Gnudi, G. Baccarani, “Investigation on superlattice heterostructures for steep-slope nanowire FETs”, Proc. DRC 2011.



E. Gnani

Recently, a junctionless (JL) NW-FET with a high content of impurity concentration within the channel and source/drain (S/D) regions has been proposed, and a device model based on the abrupt depletion approximation has been worked out [14], [15]. Soon after, a JL silicon-on-insulator (SOI) FET was fabricated and characterized by the Tyndall group [16]–[18]. The idea behind this device is that of drastically simplifying the S/D engineering by removing the related junctions, as well as the S/D extension regions while, at the same time, appropriately sizing the silicon thickness and the doping density in order to allow its switching on and off under the gate control. The fabricated devices exhibit excellent turn-on and output characteristics [16], [17] with a nearly ideal SS » 60 mV/dec, a large O N-current, which is quite comparable with that of an undoped channel transistor with the same geometry, a very small drain-induced barrier lowering (DIBL), and an interesting temperature behavior owing to the moderate temperature sensitivity of the carrier mobility at large impurity concentrations.

Current transport in conventional nanowire field-effect transistors (NW-FETs) has been the subject of several investigations, both analytical and numerical. Analytical models typically rely on two basic assumptions, namely, 1) an undoped semiconductor nanowire and 2) Boltzmann statistics. These assumptions allow, in fact, for a closed-form solution of Poisson’s equation which makes it possible to work out an intrinsic analytical relationship between gate voltage and surface potential. Alternatively, the assumption is taken of a completely depleted nanowire, consistently with the investigation of subthreshold slope (SS) and short-channel effects (SCE).

The purpose of the research is to investigate the theoretical foundations of the JL NW-FET with the aim to better understand the behavior of this device, to clarify the motivations for its surprisingly good properties, and to elucidate its strengths and weaknesses. Being a depletion/accumulation device with a high doping content in the channel, a nearly ideal SS is especially surprising. The model worked out here, however, does not rely on the abrupt-depletion approximation but, rather, on the linearization of the electric potential in the region where an appreciable content of electronic charge is present. In doing so, we achieve a better solution of Poisson’s equation, which allows us to obtain an accurate description of the internal potential and a continuous drain current at the transition between subthreshold and the ON state.

We model the electrical properties of the junctionless (JL) nanowire field-effect transistor (FET), which has been recently proposed as a possible alternative to the junction based FET. The analytical model worked out assumes a cylindrical geometry and is meant to provide a physical understanding of the device behavior. Most notably, it aims to clarify the motivation for its nearly ideal subthreshold slope and its excellent ON-state current while being a depletion device with lower electron mobility due to impurity scattering.

The model assumes a constant carrier mobility value and Boltzmann statistics and neglects quantum-confinement effects owing to the consideration of rather large nanowires. Poisson’s equation does not admit in this case any closed-form solution so that appropriate simplifying assumptions are taken under both depletion and accumulation conditions. The model is validated by comparison with numerical results both in subthreshold and in the ON state, and very good agreement is generally achieved.

The model clarifies a constraint binding the allowable value of the doping density per unit length and its impact on the overall device performance. The device variability and the parasitic source/drain resistances are identified as the most important limitations of the JL nanowire field-effect transistor.


Pubblications 2011

1)         E. Gnani, A. Gnudi, S. Reggiani, G. Baccarani, “Theory of the Junctionless Nanowire FET”, TED n.9, p. 2903, 2011.

2)         Sun, Y.; Yu, H.Y.; Singh, N.; Gnani, E.; Baccarani, G.; Leong, K.C.; Lo, G.Q., Kwong, D.L., “Junction-Less Stackable SONOS Memory Realized on Vertical-Si-Nanowire for 3-D Application”, Proc. IMW 2011.

3)         Gnani, E.; Gnudi, A.; Reggiani, S.; Baccarani, G.; Shen, N.; Singh, N.; Lo, G.Q.; Kwong, D.L., “Numerical investigation on the junctionless nanowire FET”, Proc. ULIS 2011.

4)         Sun, Y.; Yu, H.Y.; Singh, N.; Le, T.T.; Gnani, E.; Baccarani, G.; Leong, K.C.; Lo, G.Q.; Kwong, D.L., “Junction-less stackable SONOS memory realized on vertical-Si-nanowire for 3-D application”, Proc. VLSI-TSA 2011.

5)         Gnani, E., Reggiani, S.; Gnudi, A.; Baccarani, “A quasi-analytical model of the junctionless nanowire field-effect transistor”, Proc. ISDRS 2011.



M. Tartagni

Electronics is deeply penetrating into human life: ubiquitous computing and wireless sensor networks are now introducing their potential and power consumption has been greatly reduced by energy-aware design techniques. Even though, power supplies still mainly rely on electrochemical cells with limited stored charge and often unpractical to replace. However, the environment is an intrinsic source of low-density highly-available energy, often present either in steady or intermittent and irregular manners.

This research aims at developing energy autonomous systems being supplied by ultra-low environmental power sources, such as for example vibrations, thermal gradients, electromagnetic radiation and light.

The main focus is on the design of actively controlled power conversion circuits, which provide increased performance while operating with very low intrinsic power consumptions. The research has already produced several prototypes of energy harvesters requiring only few uW for operation and is now working on the exploitation of multiple independent sources in a scalable manner. Among the viable technologies, this research will explore the potential offered by modern CMOS integrated technologies both in circuit and system design for extending the operation of energy harvesters beyond current limits.


Pubblications 2011

1)         Romani, R. P. Paganelli, E. Sangiorgi, M. Tartagni. A Rapid Modeling and Prototyping Technique for Piezoelectric Energy Harvesting Systems. Proc. of SENSORDEVICES 2011, pp. 86-90.

2)         A. Romani, R. P. Paganelli, M. Tartagni. Fast and Reliable Modeling of Piezoelectric Transducers for Energy Harvesting Applications. PROCEDIA ENGINEERING. vol. 25, 2011, pp. 1345-1348

3)         A. Romani, R. Paganelli, E. Sangiorgi, M. Tartagni, Joint Modeling of Piezoelectric Transducers and Power Conversion Circuits for Energy Harvesting Applications. Proceedings of IEEE Sensors 2011, pp. 36-39



M. Tartagni

This research is aimed at developing new sensing architectures and circuits for applications to molecular biology and environmental monitoring.

With respect to molecular sensing, the goal of the research is to detect with high accuracy molecular events. Single molecule approaches have the advantage of avoiding averaging, enabling observation of transient intermediates and heterogeneity. Hence they might revolutionize the way many biological questions are addressed. The way followed by the project to boost the sensor sensitivity is based on using either affinity-binding paradigm employed by receptors or ion-channel paradigm. The goal is to combine efficiency of these bio-nanosensors with powerful flexibility of integrated electronics in a unique device. Being able to detect specific biological molecules at very low concentrations is a new promising area of medicine that aims to identify the onset or prediction of disease before the patient shows any symptoms. Practical challenges are on both biological side and electronic interface side. The most critical current signals in nanosensing applications are in the order of pA and in the kHz bandwidth. That means very low-noise electronic interfaces are required, with an input-referred root mean square (rms) noise as low as hundreds of fA in the kHz bandwidth.

In the field of environmental monitoring, the research is targeted to marine applications. In this area, the measurement of essential physical properties of seawater such as: salinity, temperature and depth pressure is crucial for marine environmental study. Conductivity, temperature and depth sensors (CTD) are the primary investigation tools for those parameters, providing information about climate processes. Therefore, CTD sensors act as important ecological tools, helping scientists to study the marine changes as well as aquatic organisms. The research aims at developing small, low-power CTD sensors for use in autonomous instruments like moored profilers, gliders, profiling floats and autonomous underwater vehicles. Innovative integrated interfaces for impedimetric sensors (salinity, temperature, pressure) are being developed with the aggressive constraint of very low power consumption and extreme precision. A complete microsystem architecture has been developed to interface impedimetric sensors using novel architectures based on sigma-delta conversion and lock-in techniques to achieve high-resolution performance with ultra-low power consumption using energy aware design techniques.


 Pubblications 2011

1)         M. Tartagni, M. Crescentini, and M. Bennati, “New Trends in Microelectronic Interfaces for (Bio)Chemical Sensors” at NATO ARW on “Portable chemical sensors for the rapid detection of chemical and biological agents and other weapons of terrorism”, Snogeholm castle, Lund (Sjöbo), Sweden, Jul. 2011.

2)         M. Crescentini, M. Bennati, and M. Tartagni, “Integrated and Autonomous Conductivity-Temperature-Depth (CTD) Sensors for Environmental Monitoring”, 54th IEEE Int. Midwest Symposium on Circuits and Systems, Seoul, Aug. 2011.

3)         M. Rossi, F.Thei and M. Tartagni, “An Automatic System for Bilayer Lipid Membrane Formation and Monitoring”, proceeding 2nd  International Conference on Sensor Device Technologies and Applications - SENSORDEVICES 2011, August 21-27, 2011 – Nice/Saint Laurent du Var, France.

4)         M. Crescentini, M. Bennati, M. Serafini, and M. Tartagni, “Noise Folding Reduction in Discrete-Time Current Sensing”, 20th European Conference on Circuit Theory and Design, Linköping, Sweden, Aug. 2011.



F. Filicori, A. Santarelli, R. Cignani, D. Niessen

Nonlinear modelling of active devices for microwave circuit design is quite a complex task due to the simultaneous presence of important nonlinear, reactive and parasitic effects. Different mathematical models have been proposed which can be directly identified on the basis of conventional measurements carried out by means of automatic instrumentation(Network Analyzers and DC sources/monitors). In particular, the device large-signal dynamic performance is computed using large-signal predictive formulae on the bases of pulsed I/V characteristics and frequency/bias dependent AC measurements stored in suitable look-up tables. Dedicated algorithms for the approximation/interpolation of nonlinear device characteristics based on a look-up table description are currently under study.

The models have been applied for the large-signal dynamic performance prediction of different types of electron devices (single- and dual-gate MESFETs, HEMTs, BJTs, HBTs etc..).

The developed models take into account low-frequency dispersive effects, due to the presence of bulk-level traps, surface states and self-heating.

In this context, different models have been developed by this research group for the accurate prediction of the dynamic drain current characteristics. In particular, the proposed models deals with the prediction of dynamic deviations of the drain current caused by thermal phenomena (e.g., device heating/cooling due to power dissipation) which can be important for relatively strong nonlinear circuits. Also the effects of ``case'' temperature variations can be taken into account once the device thermal resistance is known. The low-frequency dispersive models can be quite easily embedded both in classical nonlinear equivalent circuits and mathematical models; depending on the degree of accuracy needed, the identification of the proposed models can be based on small signal parameters, pulsed measurements large-signal low-frequency i/v characteristics under sinusoidal excitation.

Recently, a new simplified Equivalent Voltage Model (EVM) has been proposed. The EVM approach, is based on the definition of a virtually non-dispersive associated intrinsic device, controlled by means of ``equivalent'', suitably-modified voltages. By means of voltage-controlled  voltage sources, series-connected to the gate electrode, both device self-heating  and charge trapping phenomena in field effect transistors may be taken into account.  This approach allows for an easy identification procedure based on static and  small-signal, low-frequency parameter measurements which can be carried out by means of standard and low-cost instrumentation usually present  in most research laboratories.

Pubblications 2011

1)         A. Santarelli, R. Cignani, D. Niessen, S. D’Angelo, P. A. Traverso, F. Filicori, “Characterization of GaN and GaAs FETs Through a New Pulsed Measurement System”, Proc. of the 6th European Microwave Integrated Circuits conference (EuMIC 2011), pp.1-4, Oct 2011. ISBN: 978-2-87487-021-7.

2)         Raffo, V. Vadalà, P. A. Traverso, A. Santarelli, G. Vannini, F. Filicori, “A Dual-Source Nonlinear Measurement System Oriented to the Empirical Characterization of Low-Frequency Dispersion in Microwave Electron Devices”, Elsevier Computer Standards & Interfaces, Vol. 33, pp: 165-175, Anno: 2011, ISSN: 0920-5489, doi:10.1016/j.csi.2010.06.008.



F. Filicori, A. Santarelli, C. Florian, R. Cignani, D. Niessen

Simple and straightforward design methods for large-signal transistor amplifier design are investigated in this new research activity. In fact, the  availability of reliable electrical models and simulation algorithms,  specifically oriented to RF and microwave circuit design, has now opened the way to the development of efficient methodologies for power amplifier design under challenging constraints on  bandwidth,  power gain, linearity and/or efficiency.

A new simplified approach is proposed, which aims at the evaluation of the near-optimum load impedance in Class-A, quasi-linear power amplifiers for telecom applications. The search-process consists in two basic steps. First, the usual, theoretical choice for best resistive load in Class-A amplifiers, providing maximum output power, is made at the intrinsic ports of the active device; second, the corresponding extrinsic loading impedance is evaluated by investigating the mathematical relationship between the electrical variables at the intrinsic device and the scattering parameters at the extrinsic ports. Possible additional requirements on gain compression, frequency bandwidth and efficiency are compatible with the proposed approach, involving simple additional equations embedded in the Harmonic-Balance-based design environment.

The research activity is also oriented to the development of advanced design techniques and smart topology solutions for the design and implementation of hybrid and monolithic high power amplifiers for space applications. The main focus in the design of such circuits is given for the achievement of both high power and efficiency while maintaining an high reliability of the circuit. These specifications impose very tight restrictions for the device operating mode, hence only an accurate design of the amplifier with a special care on the device operating regime (dynamic load line) can lead to the exploitation of the maximum performance of the technology avoiding any reliability problem.

Finally, modelling and design of highly linear cold FET mixers has been recently addressed. This kind of mixers provides low-distortion and low phase-noise properties but poses challenging constraints on the accuracy of the FET model used in the design phase.

An equivalent voltage approach has been recently applied to the modelling of GaN-based devices in order to take into account both dispersive phenomena and nonquasi-static effects in the cold-FET operation.


Pubblications 2011

1)         C. Florian, A. Musio, F. Scappaviva, R.P. Paganelli, M. Feudale, “Design of L and X band class E power amplifiers with GaAs pHEMT technology for space SAR”, 2011 IEEE Int. RF and Micr. Conf. (RFM), 2011 , pp: 347 – 350.

2)         G. P. Gibiino, A. Santarelli, S. Farsi, M. Myslinski, G. Avolio, D. Schreurs, “S-Functions Mixer Modeling for Linearization Purpose”, Proc. of the 6th European Microwave Integrated Circuits conference (EuMIC 2011), pp. 490 – 493, Oct 2011. ISBN: 978-2-87487-021-7.

3)         L. Pantoli, G. Leuzzi, A. Santarelli, F. Filicori, R. Giofrè, “Stabilisation Approach for Multi-device Parallel Power Amplifiers under Large-signal Regime”, Proc. of the 6th European Microwave Integrated Circuits conference (EuMIC 2011), pp. 144 – 147, Oct 2011. ISBN: 978-2-87487-021-7


F. Filicori, A. Santarelli, C. Florian, R. Cignani

This research activity is mainly oriented to the development of  new design methodologies for low-phase noise Dielectric-Resonator stabilized and Voltage Controlled Oscillators (DROs and VCOs) in MMIC and MIC technology. Research efforts are actually oriented towards both the oscillator circuit design problem and the non-linear modelling of 1/f noise, G-R noise and broad-band (diffusion) noise conversion and non-linear modulation phenomena in electron devices. In particular, a new modelling approach has been proposed which allows for the inclusion, in existing "noiseless" non-linear transistor models, of non-linearly instantaneous operation-controlled noise sources which can adequately describe the phenomena of conversion and modulation of flicker, G-R and broad-band noise into RF phase-noise. Moreover a new oscillator topology has also been proposed with the aim of minimizing the non-linear phenomena which are mainly responsible for the up-conversion of low-frequency noise.

A similar approach has also been applied for the simulation of low noise amplifier noise figure in presence of an interferer signal which drives the amplifier into non-linear operation. A ciclostationary non-linear noise model which is capable of taking into account the noise sources modulation by the non-linear regime has been identified and implemented. 

Pubblications 2011

1)         R. Cignani, C. Florian, F. Filicori, G. Vannini, “Low phase noise oscillator topologies: Theory and application to MMIC VCOs” 2011 IEEE Int. RF and Micr. Conf. (RFM), 2011 , pp. 343 – 346.

2)         Florian, P. A. Traverso, F. Filicori, “The Charge-Controlled Nonlinear Noise Modeling Approach for the Design of MMIC GaAs-pHEMT VCOs for Space Applications,” IEEE Trans. on  Micr. Th. and Tech., Vol.: 59 , Issue: 4 , Part: 1  2011 , pp. 901 - 912.


F. Filicori, C. Florian

This research activity is mainly oriented to the development of special laboratory test benches for the noise characterization of electron devices.  The measurement set-ups under development are aimed at the characterization of both low-frequency noise (flicker and G-R noise) and broad-band noise (diffusion noise) of RF and microwave electron devices. Furthermore a special set-up has been implemented for the on-wafer characterization  of device LF noise up-conversion into RF phase-noise: this is achieved by forcing the device into an oscillating regime at microwave frequency.  This type of characterization is fundamental for both technology performance evaluation and identification of non-linear noise models.



F. Filicori

Collaborations: Dipartimento di Ingegneria Elettrica, Università di Bologna. Dipartimento di Elettronica, Università di Firenze. Thales Alenia Space Italy. MIUR.

The research activity in this field has been originally aimed at developing high performance instruments, based on digital signal processing techniques, for the estimation of the main parameters for signal general-purpose characterization, such as the rms value, or the power/vector spectrum. In particular, non-conventional sampling strategies, based (e.g.) on a quasi-random distribution of the sampling instants, along with suitable signal processing algorithms have been developed for the design and implementation of broad-band power meters, rms voltmeters, vector voltmeters and power/vector spectrum analyzers. The measurements carried out on laboratory prototypes of these instruments have shown good agreement with the expected performance, thus confirming the validity of the approaches proposed for architectural design, signal sampling strategies and digital data processing.

Sample/Hold (S/H) devices and Analogue-to-Digital Converters (ADCs) are clearly among the key components of this type of instruments, since their performance strongly affects the instrument overall accuracy, especially in terms of linearity and bandwidth. In order to characterize and possibly compensate all the non-idealities of different nature within these sub-systems (with particular reference to dynamic non-linearities, often not adequately taken into account by conventional methods), a behavioral approach has been developed for the non-linear dynamic modeling of the S/H-ADC cascade. The proposed methodology has been derived from a Volterra-like series expansion (namely, the Modified Volterra series) formulated for the “black-box”, technology/architecture-independent description of the system input/output relationships, which provides fast convergence and practical advantages with respect to the classical series in terms of experimental extraction feasibility/reliability and prediction accuracy under mild hypotheses on the DUT.

The modeling approach for S/H-ADC devices and, more in general, entire A/D channel architectures is being applied for the characterization and compensation of digital true rms voltmeters and oscilloscopes, the characterization/modeling of dynamic non-linearities in both stand-alone fast ADCs and ADCs within broadband, high sampling rate A/D channels for satellite radar RF receivers.

Pubblications 2011

1)         P.A. Traverso, M. Salami, G. Pasini, F. Filicori, “Characterization and modelling of broad-band GHz-field A/D acquisition channels by means of the Discrete-Time Convolution Model behavioural approach,” in: Proc. IMEKO TC-4 2011 Inter. Workshop on ADC Modelling, Testing and Data Converter Analysis and Design and IEEE 2011 ADC Forum, Orvieto, Italy, Jun.-Jul. 2011, pp. 1-6.

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