**Università degli Studi di PARMA**

Dipartimento di Ingegneria dell’Informazione

*Research topics*

**1. ANALOG, "MIXED-SIGNAL" AND RF INTEGRATED CIRCUITS**

A. Boni, C. Morandi

*Collaborations*: ST Microelectronics

**2. MODELING, CHARACTERIZATION AND RELIABILITY OF POWER DEVICES, CIRCUITS AND SYSTEMS**

P. Cova, R. Menozzi

*Collaborations*: University of Bristol, ETH Zurigo, Università of Cassino, Politecnico di Milano, Università di Padova, INFN Milano, INFN Pavia, INFN Padova, INFN Roma.

**3. THERMAL MODELING AND RELIABILITY OF SEMICONDUCTOR DEVICES**

R. Menozzi

*Collaborations*: The University of Western Australia, Università di Ferrara, IMEC

**1.**

**SIMULATION OF THIN-FILM SOLAR CELLS**

R. Menozzi

*Collaborations*: The University of Western Australia, CNR-IMEM.

**2.**

**CALIBRATION OF WEIGHTING CAPACITORS MISMATCH IN PIPELINED ADCs**

C. Morandi

*Collaborations*: G. Chiorboli, Università di Parma, GMEE

**ANALOG, "MIXED-SIGNAL" AND RF INTEGRATED CIRCUITS**

A. Boni, C. Morandi

High-speed low power A/D converters are increasingly required in telecommunications wireless and magnetic or optical data storage equipments. The Pipeline A/D converter architecture is one of the most promising solution in order to achieve high conversion speed at medium resolution.

One of the most important factors limiting the effective resolution of the pipeline converter is the capacitor mismatch affecting the linearity of the multiplier-DAC. Such errors can be removed in the digital domain by either foreground or background algorithms.

A significant research effort was focused on the foreground evaluation and compensation of DAC errors induced by weighting capacitor mismatch, taking into account a finite and inaccurately known value of op-amp gain.

Investigations of the combined application of foreground mismatch noise compensation and background gain and non-linearity calibration were carried out [1].

The research activity was focused also on the design and optimization of high resolution Sigma-Delta A/D converters. This activity was carried out in cooperation with STM, Agrate. A couple of converters was designed in 65nm CMOS technology: a 2-nd order ADC with 1-bit quantizer for sensor application, featuring a SNR higher than 100dB (simulated data) and a 2-nd order ADC with a 3-bit quantizer featuring an input bandwidth of 125kHz for radio receivers.

In the analog and RF design field the activity was focused on the design of a fully integrated temperature sensor with data processing and logging capability. The radio interface is fully compatible with the GEN-2 standard. The device was implemented in a 180nm Mixed-Signal technology and requires a supply voltage in the 1.9-1.1 V range.

*Pubblications in 2011*1) M. TONELLI, G. CHIORBOLI, C. MORANDI, ``Estimation of DAC weighting capacitors mismatch in pipelined ADCs employing finite gain op-amps'', INTERNATIONAL wORKSHOP ON ADC MODELING, TESTING AND DATA CONVERTER ANALYSIS AND DESIGN and IEEE 2011 ADC FORUM, June 30-July 1, 2011, Orvieto, Italy.

**MODELING, CHARACTERIZATION AND RELIABILITY OF POWER DEVICES, CIRCUITS AND SYSTEMS**

P. Cova, R. Menozzi

Thermal modeling of power DC/DC switching converters is carried out in the framework of a the INFN APOLLO project, aimed at designing and developing new power supplies in the LHC proton accelerator, in operation since 2010 at the European Organization for Nuclear Research (CERN) in Geneva (Switzerland). Experiments running at LHC must reliably operate in a harsh environment, due to radiation, high magnetic fields, and stringent thermal constraints. The tight performance and reliability requirements impact all the design stages, from the choice of circuit topologies and radiation hard power components, to the thermally optimized layout and choice of materials.

The role of our group is developing thermal models for the power switches and converter boards for both the Primary DC/DC converter and Point Of Load converters. Finite-Element Models (FEMs) have been built (and tuned with the aid of thermal measurements) to provide circuit designers with the knowledge necessary to tackle heat management in small sealed enclosures.

FEM was also applied to the thermal design of critical components, such as high-frequency planar transformers. The simulations allowed to evaluate the effect of frequency and output current on the temperature distribution inside the transformer, thus setting limits for reliable operation, and to analyze alternative designs aimed at improving the transformer thermal management and, consequently, its reliability.

A second activity is the development of a hybrid approach to electro-thermal modeling of power device assemblies, suitable for reliability-oriented thermal design of power modules and converters. In this approach the temperature-dependent electrical model of a power MOSFET is self-consistently coupled with a dynamic lumped-element thermal network representing the die – package – heat-sink assembly and convective boundary conditions. The lumped-element

network is built from geometrical dimensions and materials parameters. The results of the lumped-element model were successfully compared with thermal measurements under both steady-state and transient conditions.

The research unit is also involved, in cooperation with the Industrial Automation Research Unit of the University of Parma, in the design of fault tolerant digital control of high power (2 MVA), parallelable frequency converters for harbor applications. To yield a high degree of system availability the control algorithm automatically switches from parallel to single mode operation in case of fault. Scalability is another key feature of the proposed control strategy: in order to increase the output power rating, the control strategy can parallel more than two converters, increasing the availability of the whole system as well. MATLAB simulations showed that the proposed control algorithm makes the whole power system compliant with the specifications in terms of Total Harmonic Distortion (THD), power efficiency and dynamic response. A thorough measurements campaign, performed on a scaled converter prototype, confirmed the simulation results.

The research unit also cooperates with Italian companies like POSEICO SpA (Genova), GDS (Cornedo Vicentino), MOEL (Montecchio Emilia), Landi (Reggio Emilia), on specific industrial projects.

*Pubblications in 2011*1) P. Cova, N. Delmonte, F. Bertoluzza, “A software tool for the design of high power PiN diodes based on the numerical study of the reverse characteristics”,

*Solid-State Electronics*, vol. 63, pp. 60-69, 2011. ISSN: 0038-1101. doi: 10.1016/j.sse.2011.05.009

2) P. Cova, M. Bernardoni, N. Delmonte, R. Menozzi, “Dynamic electro-thermal modeling for power device assemblies”,

*Microelectronics Reliability*, vol. 51, pp. 1948-1953, 2011. ISSN: 0026-2714. doi: 10.1016/j.microrel.2011.06.016

3) P. Tenti, G. Spiazzi, S. Buso, M. Riva, P. Maranesi, F. Belloni, P. Cova, R. Menozzi, N. Delmonte, M. Bernardoni, F. Iannuzzo, G. Busatto, A. Porzio, F. Velardi, A. Lanza, M. Citterio, C. Meroni, “Power supply distribution system for calorimeters at the LHC beyond the nominal luminosity”,

*Journal of Instrumentation*, vol. 6, P6005, 2011. ISSN: 1748-0221. doi: 10.1088/1748-0221/6/06/P06005

4) M. Citterio, M. Alderighi, S. Latorre, M. Riva, P. Cova, N. Delmonte, A. Lanza, M. Bernardoni, R. Menozzi, A. Costabeber, A. Paccagnella, F. Sichirollo, G. Spiazzi, M. Stellini, P. Tenti, S. Baccaro, F. Iannuzzo, A. Sanseverino, G. Busatto, V. De Luca, “Energy distribution in hostile environment: power converters and devices”, Presented at

*13*, Villa Olmo (CO), Italy, Oct. 3-7, 2011.

^{th}International Conference on Astroparticle, Particle, Space Physics and Detectors for Physics Applications (ICATPP 2011)**THERMAL MODELING AND RELIABILITY OF SEMICONDUCTOR DEVICES**

R. Menozzi

[1] Electron device degradation, although not directly accounted for, represents a key issue in microwave circuit design. This is especially true when the particular applications involved (e.g., satellite, military, consumer) do not allow or strongly discourage any kind of maintenance. In order to account for device degradation in circuit design, there is a need for suitable electron device models able to predict performance degradation as a function of the actual electrical regime encountered in device operation. Such a kind of model is not available in the literature. In this paper, quantitative results are provided for device degradation indicators correlating DC and RF stress experiments. These results can be considered an important step toward the definition of a nonlinear model accounting for device degradation.

[2] In this paper we show results of a self-consistent large-signal electro-thermal GaN HEMT model that includes trap-related and self-heating dispersion effects. Both self-heating and trap dynamics are treated with a strictly physical approach that makes it easier to link the model parameter with the physical HEMT structure and material characteristics. The model, implemented in ADS, is applied to measured DC data taken at ambient temperatures between 200 K and 400 K, with excellent results. Several examples are given of dynamic HEMT simulation, showing the co-existence and the interaction of temperature- and trap-related dispersive effects.

[3] This work shows results of static and dynamic finite-element thermal modeling of AlGaN/GaN HEMTs highlighting the importance of boundary conditions often overlooked in simplified models. These include top-side heat removal, thermal boundary resistance between GaN and substrate, die-attach, and non-isothermal back-side. Both SiC and Si are considered as possible substrates. We also show that careful lumped-element modeling can yield thermal models accurately capturing the static and dynamic behavior without sacrificing the proper treatment of boundary conditions.

[4] This paper shows a physical approach to large-signal electro-thermal simulation of AlGaN/GaN hemts. The dynamic thermal behavior of the HEMT is described by a 3D network of thermal resistances and capacitances describing the physical structure of the HEMT, and including features such as the thermal boundary resistance between GaN and SiC, and the die-attach, as well as temperature non-uniformity along the gate finger. The thermal network is self-consistently coupled inside ADS with an electro-thermal large-signal model.

[5] In this work we show a lumped-element (LE) approach to thermal simulation of nanoscale FinFETs, which is both physics-based and suitable for insertion into circuit CAD tools. The LE modelling results match very well with finite element simulations.

[6] This work shows results of dynamic lumped-element (LE) thermal modeling of power AlGaN/GaN HEMTs. A realistic 3D structure including top-side metals, GaN-Si thermal boundary resistance, die-attach, and source via hole is modeled using a finite-element (FE) tool, and the results are used to develop simplified LE dynamic thermal models. We show that the LE models can match the FE data with excellent accuracy.

*Pubblications in 2011*1) A. Raffo, S. Di Falco, G. Sozzi, R. Menozzi, D. M.-P. Schreurs, G. Vannini, “Analysis of the gate current as a suitable indicator for FET degradation under nonlinear dynamic regime,”

*Microelectronics Reliability*, vol. 51, pp. 235-239, 2011.

2) D. Mari, M. Bernardoni, G. Sozzi, R. Menozzi, G. A. Umana-Membreno, B. D. Nener, “A physical large-signal model for GaN HEMTs including self-heating and trap-related dispersion,”

*Microelectronics Reliability*, vol. 51, pp. 229-234, 2011.

3) M. Bernardoni, N. Delmonte, R. Menozzi, “Modeling of the impact of boundary conditions on AlGaN/GaN HEMT self heating,”

*Proc. 2011 Int. Conf. Compound Semiconductor Manufacturing Technology (CS-MANTECH)*, Indian Wells, CA (USA), May 16-19, 2011, pp. 229-232, ISBN 987-1-893580-17-6.

4) M. Bernardoni, N. Delmonte, G. Sozzi, R. Menozzi, “Large-signal GaN HEMT electro-thermal model with 3D dynamic description of self-heating,”

*Proc. 41*, Helsinki, Finland, Sep. 12-16, 2011, pp. 171-174, ISBN 978-1-4577-0708-7.

^{st}European Solid-State Device Research Conf. (ESSDERC 2011)**SIMULATION OF THIN-FILM SOLAR CELLS**

R. Menozzi

Thin-film solare cells with Cu(In,Ga)Se

_{2}(CIGS) or CdTe absorbers have emerged as very promising technologies for relatively low-cost and efficient photovoltaics. Although both types of cells are already commercially produced, several aspects of their physical behavior are still to be fully understood. In particular, the influence of the grain boundaries on the electrical and optoelectronic behavior of these poly-crystalline absorbers is still a matter of debate.

[1] This paper analyzes results of numerical simulation with the aim of providing theoretical indications for Cd-free CIGS solar cell. Thickness, composition and doping of the new-material ZnMgO window layer are taken into account, together with the effects of interface states at the heterojunction ZnMgO/CIGS.

[2] Numerical modelling of polycrystalline thin film cadmium telluride (CdTe) solar cells is an important tool to understand the solar cell behaviour and to predict its efficiency. This paper models the CdTe grain boundary nanostructure by means of two-dimensional numerical simulations.

*Pubblications in 2011*1) F. Troni, G. Sozzi, R. Menozzi, “A numerical study of the design of ZnMgO window layer for Cadmium-free thin-film CIGS solar cells,”

*Proc. 7*, Madonna di Campiglio, Italia, July 3-7, 2011, pp. 193-196, ISBN 978-1-4244-9136-0.

^{th}Conf. PhD Research in Microelectronics & Electronics (PRIME 2011)**CALIBRATION OF WEIGHTING CAPACITORS MISMATCH IN PIPELINED ADCs**

C. Morandi

A correction scheme for capacitor mismatch induced error in a D/A subconverter was adapted [1] to account for the finite gain of the op-amp. The method requires rotating the weighting capacitors at each conversion step, and involves an assumption of small mismatch. It was shown by simulation that useful estimates of capacitor mismatch can be obtained even if the actual gain is replaced by a nominal gain differing by as much as a factor of two.

The scheme was then improved by removing the assumption of small mismatch.

Further extensive simulations demonstrated the feasibility of a two-step calibration, where capacitor mismatch is approximately calibrated in the foreground, at power-up, using the nominal value of the op-amp gain, then the remaining interstage gain error is calibrated in the background by means of the Keane-Hurst-Lewis interstage-gain calibration procedures, thus tracking possible gain drifts.

*Pubblications in 2011*1) M. Tonelli, G. Chiorboli, C.Morandi: “Estimation of DAC weighting capacitors mismatch in pipelined Ads employing finite gain op-amps”, 2011 International Workshop on ADC Modelling, Testing and Data Converter Analysis and Design and IEEE 2011 ADC Forum, June 30-July 1, 2011, Orvieto, Italy.