Università degli Studi di Roma La Sapienza

Dipartimento di Ingegneria dell’Informazione, Elettronica e Telecomunicazioni

Research topics

1.         Electronic systems for environmental observation and management

V. Ferrara

Collaborations: STMicroelectronics Agrate, Università di Bologna, Consorzio IU.NET


2.         Innovative structure and operation of non volatile memories

F. Irrera, R. Rao 

Collaborations: IMEC Leuven, STMicroelectronics CT, MDM Agrate, Consorzio IU.NET

3.         Reliability of advanced gate dielectrics (high-k dielectrics, ultrathin oxides, engineered barriers)

F.Irrera, R. Rao 

Collaborations: IMEC Leuven, STMicroelectronics CT, MDM Agrate, Consorzio IU.NET


4.         Performance and reliability of advanced isolations and interconnects architectures in CMOS front-end and back-end processes

F.Irrera, R. Rao

Collaborations: IMEC Leuven, STMicroelectronics CT, MDM Agrate, Consorzio IU.NET

5.         Linear and nonlinear photonic switches with liquid crystals on silicon platforms

A. D’Alessandro, R. Asquini 

Collaborations: Pennsylvania State University, IMM-CNR


6.         Integrated optical filters for fiber optic communication and sensor systems

A. d'Alessandro, R. Asquini, G. Gilardi

Collaborations: Università della Calabria, Università Politecnica delle Marche, IMM-CNR, ENEA


7.         Amorphous silicon based sensors, solar cells and electronic devices

G. de Cesare, D. Caputo

Collaborations: ENEA, IESS, EUROSOLARE, PHILIPS Aachen


8.         Lab-on-glass systems for biomolecular analysis

D. Caputo, G. de Cesare

Collaborations: Dipartimento di Genetica e Biologia Molecolare-Università di Roma "La Sapienza", DEIS-Università di Bologna



M. Balucani, A. Ferrari

Collaborations: G&A Engineering, Galileo Avionica, Philips Semiconductors, Laben, Marconi


10.     Design methodologies for low power and variation tolerant Systems-on-Chip

M. Olivieri

Collaborations: STMicroelectronics, Agrate (MI); STMicroelectronics, Catania; DEIS Univ. of Bologna; Politecnico di Torino


11.     High-level modeling approaches for propagation delay and leakge current in nano-CMOS digital cell libraries

M. Olivieri

Collaborations: STMicroelectronics, Catania; NXP, Eindhoven; Technical Univ. of Delft, The Netherlands



F. Centurelli, P. Marietti, P. Monsurrò, G. Scotti, P. Tommasino, A. Trifiletti


Collaborations: Alenia, Fondazione Bordoni, OPTO+, Philips Semiconductors, Fujitsu FCSI, Marconi, ST Microelectronics, OTI-Corning, Ericsson, IPITEC/ATMEL



F. Centurelli, P. Marietti, G. Scotti, P. Tommasino, A. Trifiletti

Collaborations: Alenia, OPTO+



F. Centurelli, P. Marietti, A. Trifiletti

Collaborations: IPITEC/ATMEL


F. Centurelli, G. Scotti, P. Tommasino, A. Trifiletti

Collaborations: Gemplus



F. Centurelli, G. Scotti, A. Trifiletti

Collaborations: Oerlikon Contraves



F. Centurelli, G. Scotti, A. Trifiletti


F.Palma, S. Perticaroli

Collaborations: Marvell PV, Politecnico Milano


Electronic systems for environmental observation and management

V. Ferrara

The electronic systems are increasingly used to analyze, observe the Earth's environment and manage natural disasters . So, early warning and disaster management need to acquire data for implementing intervention plans. Two different solutions have been proposed in literature: creation of general purpose interfaces oriented to connect remote structures, design of dedicated system oriented to environmental simulations. In order to obtain an integrated approach to the study of the environmental system and to allow an effective management of risk and the mitigation of possible hazards, we have developed a dedicated system oriented to environmental simulations and built the environmental management platform Terrapack©, able to use more recent technologies in communication and software fields.

Management of system configuration becomes the core  of structure design: complex environmental management systems are organised by means of distributed  structure, including specialised elaboration institutes of archives, communication, real-time measures, etc., and data are available in the communication network. Special care must be taken in the communication design, distinguishing between fast and slow lines.

Satellite and airborne remote sensing allow Earth observation in a integral way. Furthermore, networks of sensors at ground are used frequently both  for calibrating  remote sensing  and  for acquiring physical quantities directly in situ ground. Two services must be considered: communication and detection. Their weight is different in the two situations of early warning and emergency.  The satellite link allows to reach areas the most remote and least accessible. When communication infrastructure at ground are destroyed, the satellite link preserves continuity. In any case, an alternative sensors network at ground could be designed. It must not rely on traditional communications infrastructure and network electricity supply. This directs to device design based on energy scavenging. Consequently, each network node should be realized by meeting the design specifications of low consumption and low voltage supply. This goal can be obtained by including RF SoC founded on communication system as ZigBee. A cluster architecture of nodes network that are energetically self sufficient

Obviously, the system must be capable to resolve problems regarding: detection and measurement of parameters, organisation of data archives, connection of workstations, archive data to results intersection, efficient visualisation of results, etc.. Moreover the best supervision of environmental scenery and critical parameters must be guaranteed  to operator that deals with emergency.

We have improved our system with the inclusion of external tools (software codes of environmental simulations) which, making access to data, make their elaboration easier.


Innovative structure and operation of non volatile memories

F. .Irrera, R. Rao

Non Volatile Memory (NVM) devices, such as the Flash memories, have very simple structure consisting in a MOSFET and a control stack given by a polysilicon control gate (CG), a relatively thick dielectric which couples the control gate to the floating gate, a polysilicon floating gate (FG), and a 9-10 nm tunnel(gate) oxide.

Write/erase operation of the NVM cell is ensured by charge transfer from the substrate to the FG and vice versa. Therefore, the tunnel oxide is continuously crossed by charge.

This typically damages to the oxide and is the reason why the tunnel oxide is still thicker than 9 nm. Write/erase times and voltages depend on the mechanism used for the charge transfer. In most EEPROM cells, the write times can be in the range of microseconds by employing hot-electron injection, which, in turn, requires high voltages and currents. On the contrary, Fowler-Nordheim tunnel is a rather slow mechanism, which imposes charging/discharging times in the millisecond range and, again, requires high voltage between the FG and the substrate.

1) Tunnel programmed non-volatile memories

In our work we looked for a voltage waveform to be used in memory programming realising a good trade-off between the programming time, applied voltages and oxide degradation. The proposed solution features a small number of relatively high voltage pulses, whose parameters are determined exploiting a recent study on oxide trap dynamics under pulsed tunnelling conditions.

2) Non-volatile memories with silicon discrete storage nodes in the place of a floating gate.

Using discrete storage nodes in the place of the conventional continous polysilicon floating gate, a portion of the total charge is stored in each node. This is accompanied by a reduced loss due to the presence of SiO2 insulation between the nodes. Silicon Nanocrystals were first investigated as discrete storage nodes afterwards dielectric layers with bulk electron traps are currently under study.

3) Crested Barriers

Within the frame of alternative structures for non-volatile memories, the possibility to replace the tunnel oxide with a stack of more than one layer of dielectrics with different values of the dielectric constant was explored. Those structures aim to improve reliability of the memory while reducing the operation voltage.

Reliability of advanced gate dielectrics (high-k dielectrics, ultrathin oxides, engineered barriers)

F.Irrera, R. Rao

Systematic study of the electrical features of thin (<10 nm) and ultrathin (<5 nm) films of silicon dioxides, of degradation, soft-breakdown and hard-breakdown has furnished a consistent amount of data, useful for the development of analytical models of degradation.

The thickness of the film is a critical parameter in modeling, since it discriminates between two distinct regimes of carrier transport: scattering dominated, in the case of thin oxides, and ballistic, in the case of ultra-thin oxide. In consequence, rate equations ruling the mechanism of generation of new traps vary, and solutions give different time and field or voltage dependence. Soft-breakdown is currently being characterized in terms of Random Telegraph Noise of the gate current. 

Research in the field of high-k dielectrics started in late 2002 within the frame of National FIRB project, due to the growing interest of microelectronic industry in this field. Scaling rules of MOS transistors impose gate oxide thickness below 1 nm for incoming technology nodes. However, in the case of pure-SiO2 gate oxide, tunneling currents are too high for practical applications.

In order to overcome this problem, the use of materials with dielectric constants higher than that of SiO2 is proposed, keeping the same capacitance value and low leakage current. Oxides based on elements as zirconium, hafnium, lantanium, prasoedinium and gandolinium are currently receiving a lot of attention, since they feature good chemical stability onto silicon substrate, amorphous network, large energy gap and high band offset with silicon.

Our research is focused on the electrical characterization of zirconium and hafnium oxide grown by Atomic Layer Chemical Vapor Deposition in MOS capacitors.

The characterization is carried out by means of current-voltage curves and by capacitance-voltage, conductance-voltage measurements at different frequencies.

These measurements allow to measure the leakage current, the flat- band voltage and to estimate the defect density in the bulk oxide or at the interface.  The effect of electrical stress on reliability of dielectric films is also studied. In particular, monitoring stress induced leakage current, high-field conduction and capacitance curves as function of the injected charge, defect density (N) in the bulk oxide have been extracted by means of literature models. In particular, a square root time evolution of the stress-induced defects has been found.

More recently the high-k dielectrics have been demostrated in multilayer dielectric stacks for application as tunnel dielectric in non-volatile memories with low operation voltage, reduced equivalent thickness and not-scaled physical thickness of the tunnel oxide. In principle, the condition of not-scaled physical thickness of the tunnel oxide should prevent from data loss, if the high-k dielectric is ideal, i.e. if it exhibts density of traps of the samer order of the silicon dioxide. However, in the realty, the advantages in terms of voltages introduced by the high-dielectric must be traded-off with possible disadvantages in terms of reliability due to the distribution of traps in the bulk and at the interface with the silicon dioxide, which can degrade data retention. Reliability of such innovative structures are currently under study within a collaboration with IMEC.


Performance and reliability of advanced isolations and interconnects architectures in CMOS front-end and back-end processes

F.Irrera, R. Rao

Reduction of the transistor size is accompanied by the scaling of metal interconnections in back end. This leads to reliability problems ranging from electromigration to stress induced migration, the last being worsened by the increased complexity of the back end architecture. At the same time, shallow trench isolation in front end suffer from parasitic sidewall conduction and percolation through lateral defects, which affect performance of nanometric devices. We concentrated on simulating the structures in specific applications as CMOS image sensor and proposed new architectures devoted to solve such problems. The work was performed in strict collaboration with Micron Technology.


Linear and nonlinear photonic switches with liquid crystals on silicon platforms

A. D’Alessandro, R. Asquini

Integrated optic structures demonstrated by our group consist of channel waveguides made of E7 nematic LC in SiO2/Si V-grooves. The grooves have been obtained by wet etching n-Si  substrates first and then by thermally growing an approximately 2 µm thick SiO2 cladding layer. Propagation of infrared light at a  wavelength of 1550 nm shows a good optical confinement in 10 µm wide liquid crystal waveguides. Modal analysis and beam propagation simulations predict single mode propagation. This is experimentally confirmed by the acquired near field images. An applied electric field can control the waveguide from cut-off to multimode propagation. A single waveguide can act as an optical switch with an extinction ratio higher than 40 dB. Furthermore nonlinear effects by optically induced molecular reorientation were observed and all-optical switching was demonstrated. We are currently are studying dye-doped liquid crystal nonlinear waveguided devices in order to obtain low power all-optical integrated optic devices.

1)         M. Trotta, R. Asquini, A. dÕAlessandro, and R. Beccherelli, ÒLow power all optical rectangular liquid crystal waveguideÓ, Fotonica 2011 (13¡ Convegno Nazionale sulle tecniche fotoniche nelle telecomunicazioni), 9-11 Maggio 2011, Genova.

2)         M. Trotta, A. Piccardi, A. Alberucci, R. Asquini, A. dÕAlessandro e G. Assanto, ÒRole of material properties on NematiconsÓ, Fotonica 2011 (13¡ Convegno Nazionale sulle tecniche fotoniche nelle telecomunicazioni), 9-11 Maggio 2011, Genova.


Integrated optical filters for fiber optic communication and sensor systems

A. d'Alessandro, R. Asquini, G. Gilardi

Our group has experimentally demonstrated integrated optic filters using electro-optic gratings based on POLICRYPS structures, written on top of optical channel glass waveguides made by using double ion-exchange on glass. These optical filters have several advantages such as the optical integration, compactness, low driving voltages, short tuning times and they are switchable. The on and off state correspond to two orthogonal orientations of the LC molecule optical axis. For a  linearly polarized optical wave the LC switching corresponds to a variation of the LC refractive index equal to its birefringence of about 0.189 at 1550 nm in the case of the LC E7 (which provides a better thermal stability than 5CB). It has been observed that in such  filters it is possible to tune the filter by means of small modulations of the LC refractive index in the order of small fraction of its birefringence. Such a modulation is obtained by means of a very small modulation (of the order of a few mV) of the driving voltage, whose corresponding filter response is of a few microseconds. Our group has already demonstrated an optical filter made of a double ion-exchanged channel waveguide in BK7 glass with POLICRYPS grating, 1 cm long,  as overlayer made of alternated slices  of nematic LC E7 and UV cured polymer NOA61 by Norland. The optical filter showed a passband with about 20 dB signal suppression at the Bragg wavelength. A continuous tuning range of 4 nm was observed by applying a few tens of volt corresponding to an electric field less than 3 V/µm and with a very low current absorption resulting in a submilliwatt driving power. The  characteristics of such a filter are advantageous also for fiber Bragg grating sensor interrogating systems, as demonstrated in the  frame of our recent collaboration with ENEA laboratories in Frascati. In particular the filter resolution does not limit the sensitivity of the system, which can be in the order of 1 microstrain with a suitable design of a low noise optical receiver.Furthermore an integrated optical filter using nematic liquid crystal has been successfully designed and theoretically studied. In such a novel design the optical signal propagates through the liquid crystal and a suitable electrode configuration is able to create a liquid crystal Bragg grating, which can be widely tuned over 100 nm in the C band.An alternative integrated optic filter configuration under study consists of glass ion-exchange waveguides with quartz microspheres to select optical signals by means of whispering gallery mode approach. This technique provides very sensitive and selective filter transmission spectra.

Publications 2011

1)         R. Asquini, G. Gilardi, A. dÕAlessandro, G. Assanto, ÒIntegrated Bragg reflectors in low-index media: enabling strategies for wavelength tunability in electro-optic liquid crystalsÓ, Opt. Eng. 50, 071108 (2011).

2)         D. Donisi, L. De Sio, R. Beccherelli, M. A. Caponero, A. dÕAlessandro, C. Umeton, ÒOptical interrogation system based on holographic soft matter filterÓ, Appl. Phys. Lett. 98, 151103 (2011).

Amorphous silicon based sensors, solar cells and electronic devices

G. de Cesare, D. Caputo

Hydrogenated amorphous silicon (a-Si:H) represents the most interesting material for large area, low cost applications. Up to date, the main applications are solar cells, thin film transistor for active matrix displays and photodetectors for large area arrays. Our research is focused on the development of a-Si:H based devices for electronic and optoelectronic applications, starting from the optimization of the optical and electrical properties of the material.

- Study of the semiconductor properties: Bottom lines in this research activity are the analysis of the defect distribution and defect kinetics in the bulk material and in multi-layer structures. Different characterization methods have been developed in order to achieve informations on defects located in the forbidden gap of intrinsic, doped and compensated materials. A different defect evolution during current induced degradation and annealing of p-i-n homojunctions has been found. Nature and kinetics of defects in compensated films, deposited by a mixture of silane, phosphine and diborane gases at very low dopant concentrations, has been investigated in order to achieve materials with different optoelectronic properties with respect to intrinsic materials.

- Amorphous silicon based devices

1)      The UV Detector. We have developed and optimized a family of solar blind UV amorphous silicon photodetectors. An international patent has been carried out. Thanks to the selectivity of the device in the UV spectral range and to the measured 50% stable quantum efficiency in the vacuum ultraviolet. Applications of the UV photodetectors range from astronomical field to biomolecular analysis.

2)      The Color Detector. The two terminal bias controlled two and three color detectors have been designed in order to allow applications in large area matrix for reconstruction of bidimensional color images and for detection of labeled or naturally fuorescent molecules.

3)      The Visible Infrared Photodetector. A tunable visible/infrared amorphous/crystalline silicon heterostructure photodetector has been manufactured and characterized, showing an excellent spectral separation with few volts of bias voltage. A model has been also developed which shows a very good agreement with the measurements.

4)      The Two Terminal Switching Device. Modulation of threshold voltage of the device has been investigated, focusing on different structure parameters. Model predictions are confirmed by manufactured devices showing threshold  voltages ranging from 1 to 30 Volts, making it an alternative approach to TFT in active matrix display technology.

5)      The Bistable Device. A novel bistable device based on a-Si:H multilayer stacked structure has been manufactured and characterized. Simulation showed that the thickness and doping concentration of the central lightly doped layers determines the turn-on voltage and the width of the hysteresis of the device.

6)      The Junction Field Effect Transistor. We fabricated the first Junction Field Effect Transistor (JFET) based on a-Si:H material, which could offer the possibility to be used as switching device as well as analog amplifier. The device is constituted by a p+ -i- n- junction, with the drain and source contacts patterned on the n-doped layer and the gate electrode patterned on p+ doped layer. The manufactured device, with W/L=400/40 mm, shows the typical current-voltage curves of a JFET with a threshold voltage equal to 4 Volt.

7)      The thin film stress sensor. The device is able to perform mechanical stress measurement with both good linearity and sensitivity. A very thin film of chromium silicide is formed on the top of the doped silicon material after deposition and chemical etching of 30nm chromium film. The chromium silicide acts as active region. The device is able to measure both the bending and torsion force, depending on orientation and geometries with respect to size and location of the contacts.

8)      The UV balanced photodiode. A novel amorphous silicon balanced UV photodiode structure has been fabricated and characterized. Measured CMRR values indicate that the structure allows a good rejection of a large background radiation, making it suitable for applications where small differences in UV absorption have to be detected and large dynamic range are involved.

9)      The crystalline/ amorphous silicon heterojunction solar cell. An active collaboration on this particular project is in progress with ENEA Casaccia (Roma). Starting from the optimization of the material and of the c-Si/a-Si interface, and by using an innovative technology for the realization of the wiwndow layer, a c-Si/a-Si heterostructure solar cell has beeen fabricated, with 17% of photovoltaic conversion efficiency, that represents the highest result in heterojunction solar cell based on p-type crystalline silicon.


Lab-on-glass systems for biomolecular analysis

D. Caputo, G. de Cesare

During the last years, Lab-On-Chip (LOC) systems have shown their relevance as a powerful instrument to accomplish complex chemical or bio-chemical analysis on a single device. The functional modules included in LOC systems are those capable of sample injection, reaction, separation and detection. These analyses are commonly performed using spectroscopic, chromatographic properties or the survey of bio-luminescence or chemical-luminescence characteristics of the sample under analysis.

We are developing a compact Lab-On-Glass (LOG) system, fabricated on a conventional microscope glass slide using thin-film and thick-film technologies. The system integrates fundamental operations of the biomolecular analysis, and it is composed by three main parts.

1. The pre-treatment unit provides the thermal control by means of a thin film resistor acting as heater and an amorphous silicon diode acting as temperature sensor.

2. The sample-handling unit has the task to move the samples from the pre-treatment area to the detection unit.

3. The detection unit where the biomolecules are detected by using an a-Si:H sensor array.

The three parts of the system have been designed fabricated and characterized separately for application in DNA recognition. In particular, pre-treatment step involves a thermal cycling of the sample e.g. for DNA amplification by Polymerase Chain Reaction (PCR). The movement of DNA sample droplets from the heating chamber to the detection unit is achieved implementing the electrowetting-on-dielectric (EWOD) method. The EWOD relies on the possibility to change the contact angle of a liquid droplet in contact with a hydrophobic layer by means of an electric fields generated by an insulated control electrode, according to the Young-Lippmann equation. On chip DNA detection has been performed by using a-Si:H photosensors whose structure has been optimized to maximize the responsivity in the UV range. In particular, the device is able to detect the different absorbance of single and double stranded DNA molecules. The design of the different parts of the system has been carried out by taking into account the application requirements as well as the compatibility of the many process steps.

Application of Lab-on-glass in food quality analysis has been also implemented, taking advantage of the Thin Layer Chromatography (TLC), that is a technique commonly used for separating different compounds contained in a mixture. The unknown mixture is spotted at one end of a stationary phase, constituted by a thin layer of adsorbent (silica gel) deposited on a glass substrate (TLC plate). A liquid phase consisting in a solvent is drawn by capillarity through the stationary phase to achieve separation.

We developed a ìSMART TLC plateî which includes, on the backside of a TLC plate, a linear array of amorphous silicon p-i-n photodiodes. The basic idea is to monitor in real time the transit of the components along the stationary phase measuring the natural fluorescence of the compounds induced by UV radiation during the chromatographic run, in order to achieve quantitative information on the compounds and on their velocity along the silica gel.



M. Balucani, A. Ferrari

Our research group is involed in applied research on porous silicon technology and its applications to the microelectronic industry. Porous silicon with different morphologies has been used to realize micro- and nano-strucures and devices.

Waveguides buried in silicon, in the visible and infrared region have been demonstrated (optical waveguides loss has been measured and resulted in 0.5 dB/cm).

Silicon On Insulator (SOI), based on fully-oxidized porous silicon, with BOX (Buried OXide) thickness up to 10um has been realized.Test matrix circuit based in 1um CMOS technology were realized and characterized showing an increased performances of 20x-30x.New topology of integrated circuit for low voltage applications were realized. DTMOS (Dynamic Threshold MOS) band-gap reference voltage was realized in 0.22um bulk silicon technology showing a stable 0.85V output. New SOI PBT (Permeable Base transistor) has been simulated and developed.

Multi-layer structures based on laser ablation technique based on Si/TiN/Si for the development of vertical devices are under development. Good rectifying proprieties of TiN/Si strucutures were demonstrated.New and improved topologies for LDO regulators for mobile applications have been realized and tested in the 40nm technology node.

MEMS (Micro Electro Mechanical Systems) using porous silicon as sacrificial layer have been developed and demonstrated. New CRML (Controlled Release Metal Layer) technology has been developed for the realization of compliant electrical interconnection layers. Such layers have been applied to the realization of fine-pich probe cards and new IC packaging structures (extensive characterization of contact reliability has been performed). The same technology has been applied to the realization of the u-Helix tapered helical antennas (for GHz and THz regions). Antenna demonstrators have been simulated, built and measured in the 11GHz band (4 loops, 5 dBi gain and 70° HPBW).A new MEMS technology consisting in alternating macro- and micro-porous silicon layers has been developed, and will be applied to the realization of microfluidic channel structures. The superhydrophobicity of macroporous silicon layers realized with this technology has been measured. Metal deposition into porous silicon layers (macro- and meso-porous) has been extensively researched and optimized process for fast electrodeposition of Nickel and Copper have been developed. A new displacement deposition for Copper and Gold (the latter selective with respect to silicon) has been developed. Metal deposition into porous silicon processes have been extensively used in the CRML technology and in the realization of low conctact resistivity front side metallization for crystalline silicon solar cells. The salicidation process (forming a NiSi layer) to lower contact resistivity has been optimized. Complete conversion of porous silcon into metal, using the displacement deposition of copper, has been used for the realization of a flexible electrode for medical applications. Electrode has been realized by hot-embossing of porous metal into biocompatible polymer. Electrodeposition and displacement of copper into anodic alumina templates has been studied and copper nanorods with 30nm diameter have been formed with both processes. A new micro-thruster in silicon technology for  micro-satellites were designed and simulated in terms of mechanical and thermal stability. The micro-thruster are realized and tested.

Publications 2011

1)         Neri, F., Di Fazio, F., Teng, R., Balucani, M. A novel series-parallel inverting charge pump topology in 40nm CMOS technology (2011) 2011 IEEE International Conference on Microwaves, Communications, Antennas and Electronic Systems, COMCAS 2011, art. no. 6105825.

2)         Nenzi, P., Giacomello, A., Bolognesi, G., Chinappi, M., Balucani, M., Casciola, C.M. Superhydrophobic porous silicon surfaces (2011) Sensors and Transducers, 13 (SPEC.ISSUE), pp. 62-72.

3)         Balucani, M., Pasquale, A., Nenzi, P., Bandarenka, H., Palma, F.New technology for metal nanorods formation (2011) Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011, 2, pp. 188-191.

4)         Nenzi, P., Crescenzi, R., Klyshko, A., Bondarenko, V., Balucani, M. Compliant interconnect technology for power modules in automotive applications (2011) Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011, 2, pp. 430-433.

5)         Balucani, M., Belfiore, N.P., Crescenzi, R., Genua, M., Verotti, M. Developing and modeling a plane 3 DOF compliant micromanipulator by means of a dedicated MBS code (2011) Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011, 2, pp. 659-662.

6)         Bandarenka, H., Redko, S., Nenzi, P., Balucani, M. Copper displacement deposition on nanostructured porous silicon (2011) Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011, 2, pp. 269-272.

7)         Balucani, M., Nenzi, P., Chubenko, E., Klyshko, A., Bondarenko, V. Electrochemical and hydrothermal deposition of ZnO on silicon: From continuous films to nanocrystals (2011) Journal of Nanoparticle Research, 13 (11), pp. 5985-5997.

8)         Nenzi, P., Tripaldi, F., Balucani, M., Marzano, F.S. Three-dimensional micro-antenna array for millimetre and sub-millimetre-wave remote imaging (2011) Proceedings of the 5th European Conference on Antennas and Propagation, EUCAP 2011, art. no. 5782082, pp. 2596-2600.

9)         Balucani, M., Nenzi, P., Crescenzi, C., Marracino, P., Apollonio, F., Liberti, M., Densi, A., Colizzi, C. Technology and design of innovative flexible electrode for biomedical applications (2011) Proceedings - Electronic Components and Technology Conference, art. no. 5898682, pp. 1319-1324.

10)     Neri, F., Di Fazio, F., Crescenzi, R., Balucani, M. A novel micromachined loudspeaker topology (2011) Proceedings - Electronic Components and Technology Conference, art. no. 5898666, pp. 1221-1227.

Design methodologies for low power and variation tolerant Systems-on-Chip

M. Olivieri

Current silicon technology has made possible the integration of a complete heterogeneous system on a single silicon chip composed of interacting subsystems endowed with radically different functionalites (CPU, memory, I/O, coprocessors, analog parts, etc.).

The availability of pre-designed blocks (IP cores) allows the SoC designer to move the design effort from single components to the definition of an architecture connecting several blocks that guarantees optimum balance between performance, energy requirements and cost. Therefore, it is essential that critical block cores be designed taking into account system-level performance and power dissipation.

With this view, we are designing innovative cores in the form of programmable processors featuring special functions to reduce the power consumption.  Moreover, the variation of technology parameters impact delay and energy consumption and must be properly managed at deisgn time. Activity in this field has been done both in innovative modeling and in design.

Another important activity focus on the mapping of code on scratchpad memories for optimal reduction of total power consumption, including leakage currents. In particular it has been developed a technique for scratchpad mapping of code segments, which has the distinctive characteristic of working directly on application binaries, thus requiring no access to either the compiler or the application source code.

Publications 2011

1)         F.Menichelli, M.Olivieri, S.Smorfa “Performance evaluation of Jpeg2000 implementation on VLIW cores, SIMD cores and multi-cores”; Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, pp. 1483 - 1486


High-level modeling approaches for propagation delay and leakge current in nano-CMOS digital cell libraries

M. Olivieri

Leakage currents and technology parameter variations are the most relevant issues in digital nano-CMOS cell libraries, leading to the need for accurate predictions in the early phases of the design flow. While circuit-level Spice simulation allows the highest accuracy, it is not feasible for circuits of practical interest due to the huge computation time. A logic level model would allow a much faster evaluation. The digital research group at Sapienza University is developing logic level propagation delay models and leakage current models, which are feasible for integration in a logic level simulation (VHDL based simulation), yet showing accuracy very close to Spice.

The model of the propagation delay of nano-CMOS digital cells is a new semi-empirical one, accounting for input slope and technology parameters, featuring Spice-level accuracy and full suitability for logic level statistical timing simulation in an HDL environment. The approach is tested against Spice BSIM4 targeting a library of 272 standard cells.

The leakage calculation approach is suitable for implementation in HDL models or as an off-line tool, supporting separate estimation of the leakage components (subthreshold, gate tunneling, reverse junction BTBT) including pattern dependency, stacking effects and loading effects.

Both research activities targets the implementation of fast logic level Monte Carlo analysis of the statistical behavior of leakage and propagation delay. The two research activities are being carried out within two European projects financed by the ENIAC Joint undertaking on Nanoelectronics research.

A preliminary set of results has been obtained.

Publications 2011

1)         Mastrandrea, A.; Menichelli, F.; Olivieri, M.; “A delay model allowing nano-CMOS standard cells statistical simulation at the logic level”, Ph.D. Research in Microelectronics and Electronics (PRIME), 2011 7th Conference on, 3-7 July 2011, pp. 217–220.

2)         Abbas, Z.; Genua, V;  Olivieri, M.; “A novel logic level calculation model for leakage currents in digital nano-CMOS circuits”, Ph.D. Research in Microelectronics and Electronics (PRIME), 2011 7th Conference on, 3-7 July 2011, pp. 221-224



F. Centurelli, P. Marietti, P. Monsurrò, G. Scotti, P. Tommasino, A. Trifiletti

Our research group is involved in high-frequency IC design from a theoretical and design-oriented point of view. Our experience, which is mainly oriented to the design of multi-function modules for 10 and 40 Gb/s optical communications systems, has been established by using several GaAs and Si/SiGe processes. Both design methodologies and topologies/architectures for the different functions required in a high speed optical communication system have been developed, to overcome sensitivity to process dispersion and technology limitations.

Some of the results have been obtained in the frame of our industrial collaborations, and in particular, in collaboration with ST Microelectronics we have developed a TX-RX chip-set in SiGe BiCMOS technology that is compatible with the different international standards for 10 Gb/s optical communications (SDH, SONET, 10 Gigabit Ethernet, SDH with FEC). One focus of our research has been the development of amplifier topologies that allow to enhance the bandwidth with respect to a simple differential pair, without affecting the DC gain, so resulting in a net gain-bandwidth product increase. We have proposed a topology for a wideband amplifier based on a conventional buffered differential pair with resistive degeneration, where a positive capacitive feedback is applied to obtain a bootstrap action that results in an 'anti-pole-splitting' effect; different feedback configurations have been considered to evaluate their relative performance. Best results show about a 160% bandwidth increase with respect to a simple differential pair, and about a 30% increase relative to other widebanding methods previously proposed in the literature. Different approaches to gain-bandwidth product enhancement have been based on a single-input to differential converter cell (SID) we have developed, that exploits common-mode feedback to generate the second input to the differential pair, so doubling the gain with respect to a simple differential pair with a grounded input. The SID cell has been used to design a differential structure that reduces by a factor of two the input impedance for a given differential gain, so allowing bandwidth enhancement for high-resistance-driven differential amplifiers. Moreover, an amplifier architecture based on SID cells in a tree-like structure has been proposed that exploits additive gain with wideband interfaces.

We have also studied the application of interferometric frequency-discriminator systems (used in microwave applications) to fully-integrated Si VCO's in the low microwave range, to achieve phase noise reduction to meet system specifications for optical and wireless communication systems.

Another research field we have focused on has been the development of circuits and architectures for clock recovery from NRZ data. We have developed a novel topology for a linear phase detector to be used with a NRZ data stream, based on clock sampling by the data edges. The phase detector allows low-jitter high-speed low-voltage operation (below 2.5 V); its current-mode differential output allows an easy implementation of dual-loop frequency- and phase-locked loops for clock recovery, where the phase detector and the PFD-CP (phase- and frequency-detector with charge pump) in the frequency loop share the same output interface towards the loop filter. We have also developed a novel phase detector architecture that compensates for the sensitivity to transition density in the data pattern, allowing a more constant phase detector gain over time.

For what concerns the PFD, we have developed novel architectures that avoid the dead-zone problem (the phase detector output becomes erratic for very low phase differences) overcoming some of the limitations of typical solutions (reduced linear range, outputs with the wrong polarity, frequency limitations).

We have also focused on the development of behavioral models for fast clock recovery circuit design and simulation. We have presented an accurate empirical behavioral model of a noisy oscillator which allows simulation within CAD tools and implementation in high-level languages; the model takes into account the noncyclostationary effects of the noise sources, and is able to describe phase and amplitude noise dynamics, so allowing a fast and accurate description of the VCO in PLL system simulations. A behavioral model has been developed also for phase detectors for NRZ clock recovery applications, that allows to reproduce the output waveform of the detector taking into account dynamic effects due to high-frequency operation.


F. Centurelli, P. Marietti, G. Scotti, P. Tommasino, A. Trifiletti

Our research activity has been focused both to the development of statistical non-linear models for MESFET and HEMT GaAs devices and to the identification of techniques able to provide GaAs MMIC's yield improvement. A non-linear statistical model of MESFET and HEMT devices, in which statistical parameters are considered a gaussian multivariate random variable, has been previously identified and an automatic procedure to achieve the extraction of the statistical model parameters from a database of DC Ids and S-parameter measurements has been developed and checked on OMMIC-D02AH GaAs HEMT monolithic process. The statistical empirical non-linear model of GaAs FET devices which allows to represent distance-dependent intra-chip technological parameter variations has been implemented in HP-ADS CAD tool. The covariance matrix, which represents correlation between devices as a function of their mutual distance, has been used to develop the statistical model of an MMIC with a chosen topology. An automatic procedure to extract MMIC model parameters has been developed. The correlation matrix is orthogonalised and reduced by using the Principal Component Analysis (PCA) technique, so leading to an easy CAD implementation and simulation of the model. Hypothesis tests of equivalence have been performed to check the equivalence of statistical distributions of the measured S-parameters and the PCA-based reduced model. Validation of model and extraction procedure has been performed by comparing the covariance matrix of test-chip measured S-parameters to the one obtained from the statistical model at each frequency and for several distances between devices. The next step of our research activity has been the identification of both a control architecture and design flow able to minimize the effect of process parameters variations on MMIC performance thus providing yield improvement. The previously developed statistical non-linear model is used within the proposed design flow to simulate and optimize the yield of an MMIC in which the mutual distances between devices have been chosen. The control architecture is based on an external silicon digital controller and on a set of suitable on-chip circuits which are able to perform an on-line estimation of active devices model parameters. In particular we have studied a set of circuital topologies which can be added to the MMIC in order to estimate the DC statistical parameters of our statistical model. The digital controller uses this on-line estimation in order to provide the optimal set of bias voltages and currents for the MMIC: optimal bias as function of actual DC parameters values is previously determined by means of yield simulations and is stored in the digital controller. The effects of this control architecture have been studied from the viewpoint of design centering theory and a detailed design methodology which allows to choose the optimal set of bias voltages and currents to be stored in the digital controller has been provided. The overall yield-oriented design flow has been applied to the design of a 2.5 Gbit/s front-end amplifier showing a strong yield improvement. Measurement-based models of a Mach-Zehnder modulator and of its electrical driver have been proposed to perform their concurrent design. The models can be used to design each of the two devices when the simulated or measured performance of the other is available, as well as to simulate the performance of the overall transmitter in terms of eye-diagram at each section and of extinction ratio. The model of the driver amplifier is based on both non-linear frequency-domain measurements (or simulations) of the driver itself, and small-signal characterization of the modulator input impedance. The model has been validated for analogue applications. The modulator model is divided into three blocks: an input taper which matches the 50 Ohm electrical coplanar input to the lower impedance active region, the active L-length coplanar region where the electrooptic interaction comes, and the output taper with load termination. An empirical measurements-based model has been used to describe the propagation of the electric field within the three sections of the modulator: the time-domain voltage at position y of each of the two branches at each section is computed by means of the pulse response which is evaluated from measured S-parameters. A procedure has been developed to determine the S-parameters of the three sections of the modulator from both measurements performed on proper test-structures and e.m. simulations.

Publications 2011

1)         G. Scotti, P. Tommasino, A. Trifiletti, A. Vannucci, “A Mach-Zehnder Modulator Model for the Design of Optical-Fiber Analog Transmitters”, INMMiC 2011: Integrated Non-linear Microwave and Millimetre-wave Circuits Workshop, Vienna, 18-19 Apr. 2011.


F. Centurelli, P. Marietti, A. Trifiletti

Our research activity (performed in the framework of the MADESS Program) was directed to the development of automatic procedures for the analysis of multi-user (MU) receiver performance. Such receivers are employed in wireless applications and make use of FDMA, TDMA and CDMA multiplexing techniques. Due to its better performance if compared to TDMA and FDMA, the DS-CDMA technique has been investigated, by considering "real world" effects that might disturb the communication: impulsive and gaussian noise, fading, near-far effect, doppler effect and multiple access interference with variable user number, have been taken into account. To analyze the bit error rate (BER) and the signal to interference plus noise ratio (SINR) at the output of digital multi-user matched filter receivers, the performance of three different types of receivers, the feedback adaptive MU receiver, the Signal sub-space estimation adaptive MU receiver, the Direct matrix inversion adaptive MU receiver, have been previously simulated and, for each of them, two interference mitigation algorithms have been developed. In order to perform the implementation of the proposed interference mitigation algorithms on DSP, their robustness with respect to computation errors has been investigated. The algorithms have been modified so that the behaviour in presence of real components with finite computation accuracy has been evaluated. In particular, 32 and 16 bit fixed point representations have been simulated. The results obtained with finite accuracy simulations have allowed considerations about the influence of computation errors on the output response of the algorithms. We have found that the Recursive matrix inversion (INVR) algorithms are more sensitive to computation errors, in particular during matrix inversion. Feedback-based iterative algorithms show better response.


F. Centurelli, G. Scotti, P. Tommasino, A. Trifiletti

Security requirements need to be embedded in a standard VLSI design flow to guarantee that a fabricated cryptographic device can provide reliable performance and robustness with respect to actions directed to capture sensitive data from within the device itself. Smart card microcontroller manufacturers implement on their devices many non-standard features in order to meet security requirements with minimum performance and area penalties, using a mix of gate-level, architecture-level hardware countermeasures together with special software implementation. Recent years gave rise to a competition between secure device designers and attackers who propose more and more threatening techniques to catch sensitive data from cryptographic hardware.

We were involved in this research area in the design of a silicon device implementing three different versions of a Truly Random Number Generator (TRNG) and a hardware implementation of AES encryption standard proposed by NIST. The key features of TRNG function are bit rate and statistical quality of the produced bit-stream. We proposed different topologies aimed at increasing bit rate and reducing area consumption with respect to previously published monolithically integrated TRNG's. The devices were succesfully fabricated and tested providing both state of the art results and excellent agreement with simulations.

We implemented a measurement setup to exploit power analysis techniques on the AES processor with specific reference to Differential Power Analysis (DPA), which has been proven to be effective and easy to carry out. We started a research activity on DPA and anti-DPA techniques implemented both at gate level and at architecture level.


F. Centurelli, G. Scotti, A. Trifiletti

Our group is involved in research activity on CMOS low-frequency design, with particular emphasis on analog-to-digital converter applications.

We focus in particular on analog-to-digital converters for communication and radar systems, to be integrated in CMOS mixed-signal ICs; such ADCs usually are based on the pipeline architecture and may require calibration to guarantee high accuracy at high speed. Starting from an industrial-level design in BiCMOS tecnology, we study the ADC both from a system and circuit design point of view, focusing on two possible applications: a CMOS-only 100 MS/s 16 bit ADC and a sub-1 V ADC. This activity also requires the development of accurate behavioral models for the ADC functional blocks, to carry out fast but accurate simulation for system analysis and design. Moreover, research activity on very high-speed ADCs (flash, semiflash and folding architectures) is also carried out.



F. Centurelli, G. Scotti, A. Trifiletti

Our research group is involved in research activity on very low voltage analog circuit design and on analog design in very short channel CMOS technologies. The main focus is on circuit topologies for the basic building blocks, with a particular emphasis on differential and pseudo-differential pairs and high-gain stages. Also applications of these fuctions in practical systems such as analog-to-digital converters and active filters is considered.


F.Palma, S. Perticaroli

The research aim to develop new architectures for low noise oscillator.

In particular we pursuit the idea of refilling energy to the circuit only at times along the orbit where the sensitivity of the circuit is lower. This idea has been already  presented in literature, in particular in order to explain the positive characteristics of one of the most popular oscillator configurations: the Colpitts oscillator. Nevertheless this idea has not been extended to the differential configuration, widely adopted in integrated circuits, due to its capability to reject bias and substrate noise.

Beside this idea we also refer to the approach proposed for differential oscillators by A.A. Abidi, usually referred to as simply “noise filter”. This architecture suggests to limits the 1/f noise due to the bias current generator by the introduction of a shunt capacitor and, following, the use of a series inductor in order to limit the effect of noise of the switching transistors,

becoming relevant with the presence of the shunt capacitor and parasitic capacitance.

Developments based on the projection on the Monodromy matrix eigenvectors can be used to attempt new approaches to design of PPL . A first attempt has been carried out promising to give a relatively low complexity model (in principle analytically resolvable) which can take care of different PLL structures once a model of the loop filter is assessed.

We are also following an experimental characterization of free running  oscillators and PLL, in particular spectral distribution of the phase noise of the synthesized oscillator and jitter, and their relationship with the cyclo-stationary nature of the noise.


Ultime notizie

  • Chips-IT: open applications for the position of Director

    Chips-IT, an Italian Foundation whose mission is to advance research in Integrated Circuit design, invites applications for the position of Director Location: Pavia, Italy About Chips-IT Chips-IT was founded in...

Questo sito utilizza cookies. Continuando la navigazione si accetta di riceverli.